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| Patent # | Description |
|---|---|
| 2011/0173430 |
IT Automation Appliance Imaging System and Method A system, method, and computer program product for harvesting an image from a local disk of a managed endpoint to an image library is provided. In an embodiment... |
| 2011/0173429 |
METHOD AND APPARATUS TO MINIMIZE COMPUTER APPARATUS INITIAL PROGRAM LOAD
AND EXIT/SHUT DOWN PROCESSING A method to reduce and thereby improve the initial program load time of a computing apparatus operating system and thus provides for near instantaneous user... |
| 2011/0173428 |
COMPUTER SYSTEM, METHOD FOR BOOTING A COMPUTER SYSTEM, AND METHOD FOR
REPLACING A COMPONENT The invention relates to a computer system (1) including a system component (2) having at least one processor (5) and also at least one non-volatile memory chip... |
| 2011/0173427 |
System and Method for Personalizing Devices A system and method for personalizing a device is disclosed herein. A user configures a plurality of settings associated with a device. Each setting is... |
| 2011/0173426 |
METHOD AND SYSTEM FOR PROVIDING INFORMATION TO A SUBSEQUENT OPERATING
SYSTEM A method for transferring execution to a subsequent operating system. The method includes rebooting a computer system. Rebooting the computer system includes... |
| 2011/0173425 |
COMPUTER AND METHOD FOR MANAGING COMPUTER A computer includes a control module and a basic input and output system (BIOS) storage module. The BIOS storage module stores BIOS programs. The BIOS storage... |
| 2011/0173424 |
INTEGRATED CIRCUIT DEVICE CONFIGURATION Various embodiments include an integrated circuit (IC) device having a conductive contact, and a circuit to determine a resistance value of a circuit path... |
| 2011/0173423 |
Look-Ahead Hardware Wake-and-Go Mechanism A hardware wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism looks ahead in the instruction stream of a thread for... |
| 2011/0173422 |
PAUSE PROCESSOR HARDWARE THREAD UNTIL PIN A system and method for enhancing performance of a computer which includes a computer system including a data storage device. The computer system includes a... |
| 2011/0173421 |
MULTI-INPUT AND BINARY REPRODUCIBLE, HIGH BANDWIDTH FLOATING POINT ADDER
IN A COLLECTIVE NETWORK To add floating point numbers in a parallel computing system, a collective logic device receives the floating point numbers from computing nodes. The collective... |
| 2011/0173420 |
PROCESSOR RESUME UNIT A system for enhancing performance of a computer includes a computer system having a data storage device. The computer system includes a program stored in the... |
| 2011/0173419 |
Look-Ahead Wake-and-Go Engine With Speculative Execution A wake-and-go mechanism is provided for a microprocessor. The wake-and-go mechanism looks ahead in the instruction stream of a thread for programming idioms... |
| 2011/0173418 |
INSTRUCTION SET EXTENSION USING 3-BYTE ESCAPE OPCODE A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of... |
| 2011/0173417 |
Programming Idiom Accelerators A wake-and-go mechanism may be a programming idiom accelerator. As a processor fetches instructions, the programming idiom accelerator may look ahead to... |
| 2011/0173416 |
DATA PROCESSING DEVICE AND PARALLEL PROCESSING UNIT A data processing device in which parallel processing elements can efficiently perform processing is provided. A parallel processing module includes plural... |
| 2011/0173415 |
MULTI-CORE SYSTEM AND DATA TRANSFER METHOD According to one embodiment, each of routers includes: a cache mechanism that stores data transferred to the other routers or processor elements; and a unit... |
| 2011/0173414 |
MAXIMIZED MEMORY THROUGHPUT ON PARALLEL PROCESSING DEVICES In parallel processing devices, for streaming computations, processing of each data element of the stream may not be computationally intensive and thus... |
| 2011/0173413 |
EMBEDDING GLOBAL BARRIER AND COLLECTIVE IN A TORUS NETWORK Embodiments of the invention provide a method, system and computer program product for embedding a global barrier and global interrupt network in a parallel... |
| 2011/0173412 |
DATA PROCESSING DEVICE AND MEMORY PROTECTION METHOD OF SAME A memory protection method includes setting a memory area in at least one address setting register; setting a trap type in a trap type setting register... |
| 2011/0173411 |
TLB EXCLUSION RANGE A system and method for accessing memory are provided. The system comprises a lookup buffer for storing one or more page table entries, wherein each of the one... |
| 2011/0173410 |
EXECUTION OF DATAFLOW JOBS A method, system and computer program product for storing data in memory. An example system includes at least one multistage application configured to generate... |
| 2011/0173409 |
Secure Processing Unit Systems and Methods A hardware Secure Processing Unit (SPU) is described that can perform both security functions and other information appliance functions using the same set of... |
| 2011/0173408 |
Securing non-volatile data in an embedded memory device The various embodiments of the invention relate generally to semiconductors and memory technology. More specifically, the various embodiment and examples of the... |
| 2011/0173407 |
DATA STORAGE SYSTEM A data storage system comprising a server computer and a data storage medium. The server computer includes an interface, such as an iSCSI interface, for... |
| 2011/0173406 |
DATA PROCESSING SYSTEM HAVING A PLURALITY OF STORAGE SYSTEMS It is an object of the present invention to conduct data transfer or data copying between a plurality of storage systems, without affecting the host computer of... |
| 2011/0173405 |
SYSTEM AND METHOD FOR REDUCING LATENCY TIME WITH CLOUD SERVICES A system and method for reducing service latency includes dividing an information technology service for a customer into an infrastructure management service... |
| 2011/0173404 |
USING THE CHANGE-RECORDING FEATURE FOR POINT-IN-TIME-COPY TECHNOLOGY TO
PERFORM MORE EFFECTIVE BACKUPS A method for using a change-recording feature to perform more effective backups includes generating an initial point-in-time copy of source data residing in a... |
| 2011/0173403 |
USING DMA FOR COPYING PERFORMANCE COUNTER DATA TO MEMORY A device for copying performance counter data includes hardware path that connects a direct memory access (DMA) unit to a plurality of hardware performance... |
| 2011/0173402 |
HARDWARE SUPPORT FOR COLLECTING PERFORMANCE COUNTERS DIRECTLY TO MEMORY Hardware support for collecting performance counters directly to memory, in one aspect, may include a plurality of performance counters operable to collect one... |
| 2011/0173401 |
PRESENTATION OF A READ-ONLY CLONE LUN TO A HOST DEVICE AS A SNAPSHOT OF A
PARENT LUN A method, apparatus, and system of presentation of a read-only clone Logical Unit Number (LUN) to a host device as a snapshot of a parent LUN are disclosed. In... |
| 2011/0173400 |
BUFFER MEMORY DEVICE, MEMORY SYSTEM, AND DATA TRANSFER METHOD This invention may be applied for performing a burst write of write data, and increases efficiency of data transfer to memory. A buffer memory device transfers... |
| 2011/0173399 |
DISTRIBUTED PARALLEL MESSAGING FOR MULTIPROCESSOR SYSTEMS A method and apparatus for distributed parallel messaging in a parallel computing system. The apparatus includes, at each node of a multiprocessor network,... |
| 2011/0173398 |
TWO DIFFERENT PREFETCHING COMPLEMENTARY ENGINES OPERATING SIMULTANEOUSLY A prefetch system improves a performance of a parallel computing system. The parallel computing system includes a plurality of computing nodes. A computing node... |
| 2011/0173397 |
PROGRAMMABLE STREAM PREFETCH WITH RESOURCE OPTIMIZATION A stream prefetch engine performs data retrieval in a parallel computing system. The engine receives a load request from at least one processor. The engine... |
| 2011/0173396 |
Performing High Granularity Prefetch from Remote Memory into a Cache on a
Device without Change in Address Provided is a method, which may be performed on a computer, for prefetching data over an interface. The method may include receiving a first data prefetch... |
| 2011/0173395 |
TEMPERATURE-AWARE BUFFERED CACHING FOR SOLID STATE STORAGE A system and method for managing a cache includes monitoring a temperature of regions on a secondary storage based on a cumulative cost to access pages from... |
| 2011/0173394 |
ORDERING OF GUARDED AND UNGUARDED STORES FOR NO-SYNC I/O A parallel computing system processes at least one store instruction. A first processor core issues a store instruction. A first queue, associated with the... |
| 2011/0173393 |
CACHE MEMORY, MEMORY SYSTEM, AND CONTROL METHOD THEREFOR A cache memory according to the present invention includes: a first port for input of a command from the processor; a second port for input of a command from a... |
| 2011/0173392 |
EVICT ON WRITE, A MANAGEMENT STRATEGY FOR A PREFETCH UNIT AND/OR FIRST
LEVEL CACHE IN A MULTIPROCESSOR SYSTEM... In a multiprocessor system with at least two levels of cache, a speculative thread may run on a core processor in parallel with other threads. When the thread... |
| 2011/0173391 |
System and Method to Access a Portion of a Level Two Memory and a Level
One Memory A system and method to access data from a portion of a level two memory or from a level one memory is disclosed. In a particular embodiment, the system includes... |
| 2011/0173390 |
STORAGE MANAGEMENT METHOD AND STORAGE MANAGEMENT SYSTEM There is provided a storage management system capable of utilizing division management with enhanced flexibility and of enhancing security of the entire system,... |
| 2011/0173389 |
METHODS AND DEVICES FOR TREATING AND/OR PROCESSING DATA At the inputs and/or outputs, memories are assigned to a reconfigurable module to achieve decoupling of internal data processing and in particular decoupling of... |
| 2011/0173388 |
FIBER CHANNEL CONNECTION STORAGE CONTROLLER A storage system adapted to be coupled to a plurality of host devices via a fibre channel. The storage system including a plurality of storage devices, at least... |
| 2011/0173387 |
STORAGE SYSTEM HAVING FUNCTION OF PERFORMING FORMATTING OR SHREDDING It is desired to reduce the danger of leakage of data stored in a logical storage device. A storage system has a detection unit and a security processing unit.... |
| 2011/0173386 |
TERNARY CONTENT ADDRESSABLE MEMORY EMBEDDED IN A CENTRAL PROCESSING UNIT An arithmetic logic unit (140) improves the processing of information. The arithmetic logic unit (140) includes a register unit (250), a ternary content... |
| 2011/0173385 |
Methods And Apparatus For Demand-Based Memory Mirroring A method includes determining an amount of memory space in a memory device available for memory mirroring. The method further includes presenting the available... |
| 2011/0173384 |
Internet-Safe Computer The present invention eliminates the possibility of problems with viruses, worms, identity theft, and other hazards that may result from the connection of a... |
| 2011/0173383 |
METHODS OF OPERATING A MEMORY SYSTEM Methods of operating a memory system are useful in facilitating access to data. Where repetitive data patterns are detected among portions of received data, and... |
| 2011/0173382 |
NAND INTERFACE A NAND interface having a reduced pin count configuration, in which all command and address functions and operations of the NAND are provided serially on a... |
| 2011/0173381 |
SYSTEM AND APPARATUS FOR FLASH MEMORY DATA MANAGEMENT The system and apparatus for managing flash memory data includes a host transmitting data, wherein when the data transmitted from the host have a first time... |
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