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Patent # Description
2011/0202823 PASTING A SET OF CELLS
Pasting a set of cells is disclosed. In some embodiments, a selection of an option to paste a set of cells in a paste destination is received; and in response...
2011/0202822 System and Method for Tagging Digital Media
A method for tagging digital media is described. The method includes selecting a digital media and selecting region within the digital media. The method may...
2011/0202821 BIDDED MARKETPLACE FOR APPLICATIONS
Methods and systems for presenting application modules on a graphical display page are provided. In accordance with one embodiment, content to be displayed on a...
2011/0202820 METHOD AND SYSTEM FOR PROVIDING LOW DENSITY PARITY CHECK (LDPC) ENCODING AND DECODING
An approach is provided for processing structure Low Density Parity Check (LDPC) codes. Memory storing edge information and a posteriori probability information...
2011/0202819 Configurable Error Correction Encoding and Decoding
A system and method are disclosed performing error correction on data by a processor. Received data is demultiplexed into a first demultiplexer output and a...
2011/0202818 NON-VOLATILE MEMORY DEVICE AND OPERATION METHOD USING THE SAME
The non-volatile memory system includes a non-volatile memory and a controller. The non-volatile memory includes a data region including a sector region for...
2011/0202817 NODE INFORMATION STORAGE METHOD AND SYSTEM FOR A LOW-DENSITY PARITY-CHECK DECODER
A receiver to receive a signal associated with a low-density parity-check (LDPC) code. The receiver includes a memory device, an address generator, and an LDPC...
2011/0202816 Distributed processing LDPC (Low Density Parity Check) decoder
Distributed processing LDPC (Low Density Parity Check) decoder. A means is presented herein that includes an LDPC decoding architecture leveraging a distributed...
2011/0202815 ERROR DETECTION AND CORRECTION SYSTEM
An error detection and correction system in accordance with an embodiment comprises: an encoding unit; a syndrome calculating unit; a syndrome element...
2011/0202814 INTERLEAVING SCHEME FOR AN LDPC CODED 32 APSK SYSTEM
An approach is provided for interleaving low density parity check (LDPC) encoded bits in 32APSK modulation systems. By assigning the bits determining modulation...
2011/0202813 ERROR CORRECTION AND RECOVERY IN CHAINED MEMORY ARCHITECTURES
Electronic apparatus, systems, and methods to construct and operate the electronic apparatus and/or systems include a memory unit configured to receive data...
2011/0202812 SEMICONDUCTOR MEMORY DEVICE
According to one embodiment, a semiconductor memory device includes semiconductor memory chips in which data requested to be written. The data has one or more...
2011/0202811 TEST ACCESS PORT WITH ADDRESS AND COMMAND CAPABILITY
The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a...
2011/0202810 PULSE DYNAMIC LOGIC GATES WITH LSSD SCAN FUNCTIONALITY
A scannable pulse dynamic logic gate may include an evaluation network that evaluates dynamic inputs in response to assertion of an evaluate pulse. The evaluate...
2011/0202809 Pulse Flop with Enhanced Scan Implementation
In an embodiment, a clocked storage device such as a pulse flop is provided. The pulse flop includes a latch coupled to receive a scan data input to the pulse...
2011/0202808 REDUCED SIGNALING INTERFACE METHOD & APPARATUS
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial...
2011/0202807 LOCK STATE MACHINE OPERATIONS UPON STP DATA CAPTURES AND SHIFTS
A process of selecting alternative test circuitry within an integrated circuit enables a test access port. Scan test instruction data is loaded into an...
2011/0202806 TAM CONTROLLER CONNECTED WITH TAM AND FUNCTIONAL CORE WRAPPER CIRCUIT
A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard...
2011/0202805 Pulse Dynamic Logic Gates With Mux-D Scan Functionality
A scannable pulse dynamic logic gate may include an evaluation network that evaluates dynamic inputs in response to assertion of an evaluate pulse. The evaluate...
2011/0202804 Circuit And Method For Simultaneously Measuring Multiple Changes In Delay
A circuit and method provide built-in measurement of delay changes in integrated circuit paths. The circuit includes a digital shift register to access multiple...
2011/0202803 METHOD FOR TESTING AN ADDRESS BUS IN A LOGIC MODULE
A method for testing an address bus (14) in a logic module (10), a logic module (10), a computer program and a computer program product are described. The...
2011/0202802 Supporting Detection of Failure Event
In a mechanism for supporting detection of a failure event, history information of a system including log information of the system including plural components...
2011/0202801 Trace data priority selection
An integrated circuit 2 is provided with a data source 6 in the form of a processor executing program instructions connected via a bus interconnect 16 to a...
2011/0202800 PROGNOSTIC ANALYSIS SYSTEM AND METHODS OF OPERATION
A prognostic analysis system and methods of operating the system are provided. In particular, a prognostic analysis system for the analysis of physical system...
2011/0202799 PROCESS FOR MAKING AN ELECTRIC TESTING OF ELECTRONIC DEVICES
The disclosure relates to a process for making an electric testing of electronic devices DUT, of the type comprising the steps of: connecting at least one...
2011/0202798 REMOTE TECHNICAL SUPPORT EMPLOYING A CONFIGURABLE EXECUTABLE APPLICATION
In a remote technical support system, in response to a request for service, a user device receives an executable application from the technical support...
2011/0202797 METHOD AND SYSTEM FOR RESETTING A SUBSYSTEM OF A COMMUNICATION DEVICE
Described herein are a method, system, and computer readable medium for resetting a subsystem of a communication device. The method involves utilizing a...
2011/0202796 MICROPROCESSOR WITH SYSTEM-ROBUST SELF-RESET CAPABILITY
A microprocessor includes a bus interface unit that interfaces the microprocessor to a bus that includes a signal that, when asserted, instructs all bus agents...
2011/0202795 DATA CORRUPTION PREVENTION DURING APPLICATION RESTART AND RECOVERY
Embodiments of the present invention are directed to a method and system for draining or aborting IO requests of a failed system prior to restarting or...
2011/0202794 METHOD OF RESTORING MASTER BOOT RECORD OF STORAGE MEDIUM, STORAGE MEDIUM DRIVING DEVICE, AND STORAGE MEDIUM
A storage medium driving device including a storage medium having a user area and a non-user area, and to record master boot record information that is backed...
2011/0202793 FAILURE SYSTEM FOR DOMAIN NAME SYSTEM CLIENT
A method performed by a domain name service client includes storing DNS entries in a local cache; sending a DNS query to another device to obtain an update to...
2011/0202792 System and Methods for RAID Writing and Asynchronous Parity Computation
A computer storage management system for managing a first plurality of data storage units, the system including: (a) an asynchronous parity computation manager...
2011/0202791 STORAGE CONTROL DEVICE , A STORAGE SYSTEM, A STORAGE CONTROL METHOD AND A PROGRAM THEREOF
A storage control device and a storage control method are provided. If a first failure detector of a first controller does not detect a failure in a second...
2011/0202790 Storage Configuration
Aspects of the subject matter described herein relate to storage configuration. In aspects, an interface is used to discover the existence, capacity, and...
2011/0202789 PROCESSOR-MEMORY UNIT FOR USE IN SYSTEM-IN-PACKAGE AND SYSTEM-IN-MODULE DEVICES
An apparatus and method for a processor-memory unit for use in system-in-package (SiP) and system-in-package (SiP) integrated circuit devices. The apparatus...
2011/0202788 METHOD AND DEVICE FOR CLOCK GATE CONTROLLING
A method and an activity tracking device for controlling clock gating of a data processing block is provided. The processing block is one of a plurality of data...
2011/0202787 Single Wire Serial Interface
A single wire serial interface for power ICs and other devices is provided. To use the interface, a device is configured to include an EN/SET input pin. A...
2011/0202786 Stalling synchronisation circuits in response to a late data signal
A data processing circuitry for processing data is disclosed. The data processing circuitry comprises: a plurality of synchronisation circuits for capturing and...
2011/0202785 METHOD AND DEVICE FOR SYNCHRONIZING DATA BROADCASTS
A method and a device for synchronizing broadcast of streaming data by a transmitting data processing unit to a plurality of receiving data processing units is...
2011/0202784 POWER SUPPLY SYSTEM, POWERED DEVICE, AND POWER RECEPTION METHOD
Power sourcing equipment starts power supply after outputting a detection signal to a transmission line and detecting that a powered device is connected with...
2011/0202783 LOW COST AND FLEXIBLE ENERGY MANAGEMENT SYSTEM CONFIGURED IN A UNITARY HOUSING HAVING A DISPLAYLESS CONFIGURATION
A device configured in a unitary displayless housing, including a computing device that stores, manipulates and communicates energy data, and the displayless...
2011/0202782 ARCHITECTURE INCORPORATING CONFIGURABLE CONTROLLER FOR REDUCING ON CHIP POWER LEAKAGE
The present invention provides a method and system for controlling leakage power consumption at a System on Chip (SoC) level during a normal run or a boot-up...
2011/0202781 System and Method for Loop Timing Update of Energy Efficient Physical Layer Devices Using Subset Communication...
A system and method for loop timing update of energy efficient physical layer devices using subset communication techniques. During a quiet period during which...
2011/0202780 DATA WRITING METHOD FOR NON-VOLATILE MEMORY, AND CONTROLLER AND STORAGE SYSTEM USING THE SAME
A data writing method for writing data from a host system into a plurality of memory dies of a rewritable non-volatile memory storage apparatus is provided. The...
2011/0202779 METHOD AND SYSTEM FOR MONITORING MODULE POWER STATUS IN A COMMUNICATION DEVICE
A method for monitoring operating status of a device includes receiving within a chip, a plurality of signals, each of the plurality of signals being indicative...
2011/0202778 METHOD AND APPARATUS FOR MANAGING POWER FROM A SEQUESTERED PARTITION OF A PROCESSING SYSTEM
A processing system may include a first processing unit for a legacy partition and a second processing unit for a sequestered partition. In one embodiment, a...
2011/0202777 Power Module for Information Handling System and Methods Thereof
An information handling system can receive power from a wireless or wired power source. In response to determining the information handling system is coupled to...
2011/0202776 Storage Device Content Authentication
Systems and methods that support storage device content authentication are provided. A system that verifies storage device content received from a storage...
2011/0202775 ATOMIC HASH INSTRUCTION
A method for performing a hash operation, including providing an atomic hash instruction that directs a microprocessor to perform a the hash operation and to...
2011/0202774 System for Collection and Longitudinal Analysis of Anonymous Student Data
A method and system for aggregating and anonymizing student data is disclosed. A method includes receiving from an educational institution a set of student data...
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