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Patent # Description
2011/0241218 Electronic Device and Manufacturing Method
A semiconductor package includes a semiconductor chip, an encapsulant embedding the semiconductor chip, first contact pads on a first main face of the...
2011/0241217 Multi-Layer Interconnect Structure for Stacked Dies
A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of...
2011/0241216 Semiconductor device
A semiconductor device includes a substrate over which a circuit is formed, a multi-layer wiring layer having a plurality of wiring layers formed over the...
2011/0241215 EMBEDDED SEMICONDUCTIVE CHIPS IN RECONSTITUTED WAFERS, AND SYSTEMS CONTAINING SAME
A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are...
2011/0241214 Virtually Substrate-less Composite Power Semiconductor Device and Method
A virtually substrate-less composite power semiconductor device (VSLCPSD) and method are disclosed. The VSLCPSD has a power semiconductor device (PSD), a...
2011/0241213 Silicide Contact Formation
A method for forming a silicide contact includes depositing a metal layer on silicon such that the metal layer intermixes with the silicon to form an intermixed...
2011/0241212 STRESS LAYER STRUCTURE
A stress layer structure includes an active stress portion and a dummy stress portion, both formed of a stress material and disposed on the substrate. The...
2011/0241211 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device has forming, in a dielectric film, a first opening and a second opening located in the first opening, forming a...
2011/0241210 COMPOSITION FOR SEALING SEMICONDUCTOR, SEMICONDUCTOR DEVICE, AND PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE
The invention provides a composition for sealing a semiconductor, the composition being able to form a thin resin layer, suppress the diffusion of a metal...
2011/0241209 Substrate comprising alloy film of metal element having barrier function and metal element having catalytic power
It is an object of the present invention to provide a layer having a barrier function and catalytic power and excelling in formation uniformity and coverage of...
2011/0241208 MICROELECTRONIC PACKAGE CONTAINING SILICON CONNECTING REGION FOR HIGH DENSITY INTERCONNECTS, AND METHOD OF...
A microelectronic package comprises a substrate (110), a silicon patch (120) embedded in the substrate, a first interconnect structure (131) at a first location...
2011/0241207 DUMMY SHOULDER STRUCTURE FOR LINE STRESS REDUCTION
Semiconductor integrated circuit line structures for improving a process window in the vicinity of dense-to-isolated pattern transition areas and a technique to...
2011/0241206 SEMICONDUCTOR DEVICE
A semiconductor device is provided by the present invention. The semiconductor device includes a first semiconductor die comprising at least a first bond pad;...
2011/0241205 SEMICONDUCTOR WITH THROUGH-SUBSTRATE INTERCONNECT
Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor...
2011/0241204 Semiconductor device
A semiconductor device includes an electrode pad provided on a semiconductor chip, in which the electrode pad includes aluminum (Al) as a major constituent and...
2011/0241203 SEMICONDUCTOR MODULE, METHOD FOR MANUFACTURING SEMICONDUCTOR MODULE, AND PORTABLE APPARATUS
A semiconductor module includes a device mounting board and a semiconductor device. The semiconductor device and the device mounting board are flip-chip...
2011/0241202 Dummy Metal Design for Packaging Structures
An integrated circuit structure includes a semiconductor chip, a metal pad at a major surface of the semiconductor chip, and an under-bump metallurgy (UBM) over...
2011/0241201 Radiate Under-Bump Metallization Structure for Semiconductor Devices
An under-bump metallization (UBM) structure for a semiconductor device is provided. The UBM structure has a center portion and extensions extending out from the...
2011/0241200 ULTRA LOW DIELECTRIC CONSTANT MATERIAL WITH ENHANCED MECHANICAL PROPERTIES
An ultra low dielectric constant material is disclosed. The ultra-low dielectric constant material comprises a three dimensional random network porous...
2011/0241199 PROGRAMMABLE SYSTEM IN PACKAGE
Some embodiments of the invention provide a programmable system in package ("PSiP"). The PSiP includes a single IC housing, a substrate and several IC's that...
2011/0241198 Power Semiconductor Module
In a power semiconductor module, a semiconductor device including electrode surfaces for connection on its front side and back side is connected on its back...
2011/0241197 Device and Method for Manufacturing a Device
A device includes a first semiconductor chip and a first encapsulant that encapsulates the first semiconductor chip and that includes a cavity. A carrier and an...
2011/0241196 COMPLIANT SPRING INTERPOSER FOR WAFER LEVEL THREE DIMENSIONAL (3D) INTEGRATION AND METHOD OF MANUFACTURING
The present invention is an apparatus for integrating multiple devices. The apparatus includes a substrate having a first via and a second via, a semiconductor...
2011/0241195 FORMING IN-SITU MICRO-FEATURE STRUCTURES WITH CORELESS PACKAGES
Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a...
2011/0241194 Stacked Semiconductor Device Package Assemblies with Reduced Wire Sweep and Manufacturing Methods Thereof
An embodiment of a stacked package assembly includes: (1) a first semiconductor device package including: (a) a semiconductor device including back and lateral...
2011/0241193 Semiconductor Device Packages with Fan-Out and with Connecting Elements for Stacking and Manufacturing Methods...
An embodiment of a semiconductor device package includes: (1) an interconnection unit including a patterned conductive layer; (2) an electrical interconnect...
2011/0241192 Wafer-Level Semiconductor Device Packages with Stacking Functionality
Described herein are wafer-level semiconductor device packages with stacking functionality and related stacked package assemblies and methods. In one...
2011/0241191 SEMICONDUCTOR LAMINATION PACKAGE AND METHOD OF PRODUCING SEMICONDUCTOR LAMINATION PACKAGE
A semiconductor lamination package includes a first package with a first semiconductor chip mounted thereon and a second package with a second semiconductor...
2011/0241190 Semiconductor Package
A method of manufacturing a semiconductor package includes providing a carrier and attaching at least one semiconductor piece to the carrier. An encapsulant is...
2011/0241189 APPARATUS FOR AND METHODS OF ATTACHING HEAT SLUGS TO PACKAGE TOPS
A frame includes heat slug pads coupled together in a N.times.M matrix such that singulation of the heat slug pads consists of one or more passes across the...
2011/0241188 GRANULAR EPOXY RESIN COMPOSITION FOR ENCAPSULATING SEMICONDUCTOR, SEMICONDUCTOR DEVICE USING THE SAME AND...
Disclosed is a granular epoxy resin composition for encapsulating a semiconductor used for a semiconductor device obtained by encapsulating a semiconductor...
2011/0241187 LEAD FRAME WITH RECESSED DIE BOND AREA
A lead frame having a recessed die bond area. The lead frame has top and bottom surfaces and a first lead frame thickness defined as the distance between the...
2011/0241186 FORMING METAL FILLED DIE BACK-SIDE FILM FOR ELECTROMAGNETIC INTERFERENCE SHIELDING WITH CORELESS PACKAGES
Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a...
2011/0241185 SIGNAL SHIELDING THROUGH-SUBSTRATE VIAS FOR 3D INTEGRATION
A shielded through-substrate via (TSV) structure includes a first through-substrate via configured to transmit a signal at least from a top surface of a...
2011/0241184 INTEGRATED CIRCUIT DEVICES HAVING SELECTIVELY STRENGTHENED COMPOSITE INTERLAYER INSULATION LAYERS AND METHODS...
An integrated circuit device includes a plurality of stacked circuit layers, at least one of the plurality of circuit layers including a composite interlayer...
2011/0241183 STACKED CHIP PACKAGE WITH REDISTRIBUTION LINES
A chip package comprises a first chip having a first side and a second side, wherein said first chip comprises a first pad, a first trace, a second pad and a...
2011/0241182 DIE SEAL RING
An improved die seal ring is described which includes at least one break. In the region of the break in the die seal ring, the doping is modified so that the...
2011/0241181 SEMICONDUCTOR DEVICE WITH A CONTROLLED CAVITY AND METHOD OF FORMATION
A semiconductor device includes a first cap wafer having a first opening extending through the first cap wafer, and a second cap wafer bonded to the first cap...
2011/0241180 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE, METHOD FOR DETECTING A SEMICONDUCTOR SUBSTRATE AND...
A method for manufacturing a semiconductor device, includes: preparing a semiconductor substrate with a first notch; preparing a supporting substrate with a...
2011/0241179 DIFFUSION REGION ROUTING FOR NARROW SCRIBE-LINE DEVICES
The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in...
2011/0241178 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
An organic protective film 23' is formed on the periphery of a chip region 12 on a substrate 11 so as to continuously surround the internal part of the chip...
2011/0241177 Semiconductor wafer including cracking stopper structure and method of forming the same
A semiconductor includes a semiconductor substrate having a main face, the semiconductor device having a device region and a dicing line and a stack of...
2011/0241176 Substrate Bonding with Bonding Material Having Rare Earth Metal
A microchip has a bonding material that bonds a first substrate to a second substrate. The bonding material has, among other things, a rare earth metal and...
2011/0241175 HARDMASK COMPOSITION FOR FORMING RESIST UNDERLAYER FILM, PROCESS FOR PRODUCING A SEMICONDUCTOR INTEGRATED...
A hardmask composition for forming a resist underlayer film, a process for producing a semiconductor integrated circuit device, and a semiconductor integrated...
2011/0241174 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
Provided is a semiconductor device manufacturing method wherein the following steps are performed; a step of forming at least a part of an element on a base...
2011/0241173 RESIST PATTERN FORMATING METHOD
The present invention provides a pattern formation method capable of preventing formation of surface defects. In the method, a resist surface after subjected to...
2011/0241172 Charge Balance Techniques for Power Devices
A silicon wafer includes a silicon region of first conductivity type and a plurality of strips of second conductivity type pillars extending in parallel in the...
2011/0241171 Method of fabricating semiconductor integrated circuit device and semiconductor integrated circuit device...
Provided are a method of fabricating a semiconductor integrated circuit device and a semiconductor integrated circuit device fabricated using the method. The...
2011/0241170 MONOLITHIC SEMICONDUCTOR SWITCHES AND METHOD FOR MANUFACTURING
One aspect is monolithic semiconductor switches and method for manufacturing. One embodiment provides a semiconductor die with a first n-type channel FET and a...
2011/0241169 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
A capacitor having a cylindrical shape is increased in capacitance, and a high-resistance region is prevented from being formed in a lower electrode. A...
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