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| Patent # | Description |
|---|---|
| 2011/0241118 |
METAL GATE FILL BY OPTIMIZING ETCH IN SACRIFICIAL GATE PROFILE A high-k metal gate electrode is formed with reduced gate voids. An embodiment includes forming a replaceable gate electrode, for example of amorphous silicon,... |
| 2011/0241117 |
Semiconductor Device Comprising Metal Gate Structures Formed by a
Replacement Gate Approach and eFuses... In a replacement gate approach for forming high-k metal gate electrode structures, electronic fuses may be provided on the basis of a semiconductor material in... |
| 2011/0241116 |
FET with FUSI Gate and Reduced Source/Drain Contact Resistance A method for forming a field effect transistor (FET) includes forming a gate stack on a silicon layer, the gate stack comprising a gate polysilicon on top of a... |
| 2011/0241115 |
Schottky Junction Source/Drain FET Fabrication Using Sulfur or Flourine
Co-Implantation A Schottky field effect transistor (FET) includes a gate stack located on a silicon on insulator (SOI) layer, the gate stack comprising a gate silicide region;... |
| 2011/0241114 |
HIGH VOLTAGE MOS TRANSISTOR A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS) and a method of making it are provided in this disclosure. The device includes a... |
| 2011/0241113 |
Dual Gate LDMOS Device with Reduced Capacitance A transistor includes an n-well implanted in a substrate, a source region including a p-body region in the n-well, and a n+ region and a p+ region in the p-body... |
| 2011/0241112 |
LDMOS Device with P-Body for Reduced Capacitance A transistor includes an n-well implanted in a substrate, a source region including a p-body region, a n+ region and a p+ region in the p-body region, a drain... |
| 2011/0241111 |
SEMICONDUCTOR DEVICE Investigation of problems of the device structure of a power MOSFET and mass production of it in relation to high breakdown voltage and low ON resistance when... |
| 2011/0241110 |
TERMINAL STRUCTURE FOR SUPERJUNCTION DEVICE AND METHOD OF MANUFACTURING
THE SAME A terminal structure for superjunction device is disclosed. The terminal structure comprises from inside out at least one P type implantation ring and several P... |
| 2011/0241109 |
Power NLDMOS array with enhanced self-protection In a self protected NLDMOS array, a deep implant is included on the drain side of each NLDMOS device to balance ESD current. |
| 2011/0241108 |
LDMOS With No Reverse Recovery A transistor includes a source region including a first impurity region implanted into a substrate, a drain region including a second impurity region implanted... |
| 2011/0241107 |
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Disclosed are a semiconductor device with a metal gate and a method of manufacturing the same. The method of the present invention includes: preparing a... |
| 2011/0241106 |
SEMICONDUCTOR DEVICE WITH BURIED GATES AND METHOD FOR FABRICATING THE SAME A semiconductor device includes a supplementary layer and a silicon layer stacked over a substrate, a trench penetrating the supplementary layer and the silicon... |
| 2011/0241105 |
SEMICONDUCTOR MEMORY DEVICE A semiconductor memory device positioned on an SOI substrate. A semiconductor memory device includes two transistors with three terminals which serve as a... |
| 2011/0241104 |
INTEGRATED CIRCUIT DEVICE AND METHOD FOR ITS PRODUCTION An integrated circuit device includes a semiconductor body fitted with a first electrode and a second electrode on opposite surfaces. A control electrode on an... |
| 2011/0241103 |
METHOD OF MANUFACTURING A TUNNEL TRANSISTOR AND IC COMPRISING THE SAME A method of manufacturing a tunnel field effect transistor is disclosed. The method comprises forming a two-step profile in a silicon substrate (100) using a... |
| 2011/0241102 |
SEMICONDUCTOR DEVICES INCLUDING BIT LINE CONTACT PLUG AND BURIED CHANNEL
ARRAY TRANSISTOR, METHODS OF... A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active... |
| 2011/0241101 |
SEMICONDUCTOR MEMORY ELEMENT AND SEMICONDUCTOR MEMORY DEVICE According to one embodiment, a semiconductor memory element includes a semiconductor layer, a tunnel insulator provided on the semiconductor layer, a charge... |
| 2011/0241100 |
STACKED NON-VOLATILE MEMORY DEVICE AND METHODS FOR FABRICATING THE SAME A stacked non-volatile memory device comprises a plurality of bit line and word line layers stacked on top of each other. The bit line layers comprise a... |
| 2011/0241099 |
SEMICONDUCTOR DEVICE INCLUDING TRANSISTOR AND FUSE CIRCUIT AND
SEMICONDUCTOR MODULE INCLUDING THE SAME A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, a first node impurity region, a second node impurity region, a... |
| 2011/0241098 |
3D STACKED ARRAY HAVING CUT-OFF GATE LINE AND FABRICATION METHOD THEREOF A three-dimensional stacked flash memory array having cut-off gate line and a fabricating method of the same are provided. The flash memory array enables to... |
| 2011/0241097 |
Semiconductor device and manufacturing method thereof Device isolation regions for isolating a device forming region are formed over a substrate. Subsequently, a gate insulation film is formed over the device... |
| 2011/0241096 |
ISOLATION REGIONS Methods and apparatus are provided. An isolation region is formed by lining a trench formed in a substrate with a first dielectric layer by forming the first... |
| 2011/0241095 |
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME In one embodiment, a semiconductor memory device, including a memory cell having a floating gate electrode above a semiconductor substrate via a first gate... |
| 2011/0241094 |
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME According to one embodiment, a semiconductor memory device includes each of memory cells including a floating electrode above a semiconductor substrate via the... |
| 2011/0241093 |
SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME A dual channel transistor includes a semiconductor island isolated by a first shallow trench isolation (STI) extending along a first direction and a second STI... |
| 2011/0241092 |
ELECTRONIC DEVICE WITH CAPCITIVELY COUPLED FLOATING BURIED LAYER Transistors (21, 41) employing floating buried layers (BL) (72) may exhibit transient breakdown voltage (BVdss).sub.TR significantly less than (BVdss).sub.DC.... |
| 2011/0241091 |
CONTROLLING FERROELECTRICITY IN DIELECTRIC FILMS BY PROCESS INDUCED
UNIAXIAL STRAIN A method of controlling ferroelectric characteristics of integrated circuit device components includes forming a ferroelectrically controllable dielectric layer... |
| 2011/0241090 |
HIGH FULL-WELL CAPACITY PIXEL WITH GRADED PHOTODETECTOR IMPLANT Embodiments of a process for forming a photodetector region in a CMOS pixel by dopant implantation, the process comprising masking a photodetector area of a... |
| 2011/0241089 |
SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING SOLID-STATE IMAGING
DEVICE, AND ELECTRONIC APPARATUS Disclosed herein is a solid-state imaging device including: a semiconductor region of a second conductivity type which is formed on a face side of a... |
| 2011/0241088 |
FIELD EFFECT TRANSISTOR, METHOD OF MANUFACTURING FIELD EFFECT TRANSISTOR,
AND METHOD OF FORMING GROOVE A field effect transistor includes a high resistance layer on a substrate, a semiconductor operation layer that is formed on the high resistance layer and... |
| 2011/0241087 |
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE A gate insulating film is formed on a substrate. Next, a gate electrode film is formed on the gate insulating film. A mask film is formed on a portion of the... |
| 2011/0241086 |
ALUMINUM FUSES IN A SEMICONDUCTOR DEVICE COMPRISING METAL GATE ELECTRODE
STRUCTURES In sophisticated semiconductor devices, electronic fuses may be provided on the basis of a replacement gate approach by using the aluminum material as an... |
| 2011/0241085 |
DUAL SIDEWALL SPACER FOR SEAM PROTECTION OF A PATTERNED STRUCTURE A semiconducting device with a dual sidewall spacer and method of forming are provided. The method includes: depositing a first spacer layer over a patterned... |
| 2011/0241084 |
Semiconductor Device with a Buried Stressor A semiconductor device, such as a PMOS or NMOS device, having localized stressors is provided. Recesses are formed on opposing sides of a gate electrode. A... |
| 2011/0241083 |
SEMICONDUCTOR DEVICE AND METHOD Transistors (21, 41) employing floating buried layers may be susceptible to noise coupling into the floating buried layers. In IGFETS this is reduced or... |
| 2011/0241082 |
DOUBLE-SIDED INTEGRATED CIRCUIT CHIPS A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having... |
| 2011/0241081 |
METHODS AND APPARATUS FOR MEASURING ANALYTES USING LARGE SCALE FET ARRAYS Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS... |
| 2011/0241080 |
SOLID-STATE IMAGING DEVICE, METHOD FOR MANUFACTURING THE SAME, AND
ELECTRONIC APPARATUS Disclosed herein is a solid-state imaging device, including a plurality of unit pixels, wherein the plurality of unit pixels include: a photoelectric conversion... |
| 2011/0241079 |
SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING SOLID-STATE IMAGING
DEVICE, AND ELECTRONIC APPARATUS Disclosed herein is a solid-state imaging device including a photoelectric conversion element operable to generate electric charge according to the amount of... |
| 2011/0241078 |
Stacked Bit Line Dual Word Line Nonvolatile Memory An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level... |
| 2011/0241077 |
INTEGRATED CIRCUIT 3D MEMORY ARRAY AND MANUFACTURING METHOD A 3D memory device is based on an array of conductive pillars and a plurality of patterned conductor planes including left side and right side conductors... |
| 2011/0241076 |
P-type Field-Effect Transistor and Method of Production An n-layer is arranged above a substrate, which can be GaAs, and a p-layer (4) is arranged on the n-layer. The p-layer is separated by a gate electrode into two... |
| 2011/0241075 |
BIPOLAR TRANSISTOR A bipolar transistor includes: a substrate; a collector and a base layer with a p-conductive-type, an emitter layer with an n-conductive-type. The collector... |
| 2011/0241074 |
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME A GaN layer and an n-type AlGaN layer are formed over an insulating substrate, and thereafter, a gate electrode, a source electrode and a drain electrode are... |
| 2011/0241073 |
STRUCTURE FOR SELF-ALIGNED SILICIDE CONTACTS TO AN UPSIDE-DOWN FET BY
EPITAXIAL SOURCE AND DRAIN A method for fabricating an upside-down p-FET includes: fully etching source and drain regions in a donor substrate by etching a silicon-on-insulator layer... |
| 2011/0241072 |
SEMICONDUCTOR STRUCTURE HAVING AN ELOG ON A THERMALLY AND ELECTRICALLY
CONDUCTIVE MASK A semiconductor structure includes a substrate, a thermally and electrically conductive mask positioned upon the substrate, and an epitaxial lateral over growth... |
| 2011/0241071 |
Semiconductor Devices Having Field Effect Transistors With Epitaxial
Patterns in Recessed Regions A semiconductor device includes a device isolation pattern, a gate line, and an epitaxial pattern. The device isolation pattern is disposed in a semiconductor... |
| 2011/0241070 |
AVALANCHE PHOTODIODE AND METHOD FOR MANUFACTURING THE AVALANCHE PHOTODIODE An avalanche photodiode including a first electrode; and a substrate including a first semiconductor layer of a first conduction type electrically connected to... |
| 2011/0241069 |
Low side zener reference voltage extended drain SCR clamps In an ultra high voltage lateral DMOS-type device (UHV LDMOS device), a central pad that defines the drain region is surrounded by a racetrack-shaped source... |
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