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Patent # Description
2011/0298083 SOI WAFER, METHOD FOR PRODUCING SAME, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
An SOI wafer including: a supporting substrate 1; a BOX layer 2 provided above the supporting substrate 1, the BOX layer 2 being formed by a thermal...
2011/0298082 SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF DRIVING THE SAME
A transistor causes fluctuation in the threshold and mobility due to the factor such as fluctuation of the gate length, the gate width, and the gate insulating...
2011/0298081 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor substrate, a surface electrode formed on the semiconductor substrate, an ineffective region formed to surround...
2011/0298080 METHOD FOR MANUFACTURING THERMOELECTRIC CONVERSION MODULE, AND THERMOELECTRIC CONVERSION MODULE
There is provided a method for manufacturing a thermoelectric conversion module that can yield a thermoelectric conversion module with a high insulating...
2011/0298079 SEMICONDUCTOR ELEMENT AND SOLID-STATE IMAGING DEVICE
A semiconductor element includes: a p-type semiconductor region; an n-type light-receiving surface buried region buried in the semiconductor region; an n-type...
2011/0298078 METHOD FOR PRODUCTION OF SOLID-STATE IMAGING ELEMENT, SOLID-STATE IMAGING ELEMENT, AND IMAGING APPARATUS
Disclosed herein is a method for producing a solid-state imaging element which has pixels, each including a sensor section that performs photoelectric...
2011/0298077 METHODS OF FABRICATION OF PACKAGE ASSEMBLIES FOR OPTICALLY INTERACTIVE ELECTRONIC DEVICES AND PACKAGE...
Packaging assemblies for optically interactive devices and methods of forming the packaging assemblies in an efficient manner that eliminates or reduces the...
2011/0298076 PHOTODIODE AND PHOTODIODE ARRAY
A p.sup.- type semiconductor substrate 20 has a first principal surface 20a and a second principal surface 20b opposed to each other and includes a...
2011/0298075 Lens Unit, Aligning Method, Image Pickup Device and Method for Manufacturing Image Pickup Device
Provided is a lens unit (3) wherein a plurality of wafer lenses (10, 20) are layered and covered by cover package (30). In each of wafer lenses (10, 20), resin...
2011/0298074 SOLID-STATE IMAGING ELEMENT AND ELECTRONIC INFORMATION DEVICE
A solid-state imaging element according to the present invention includes a plurality of light receiving sections formed in a pixel array, each light receiving...
2011/0298073 IMAGE SENSOR DEVICES AND METHODS FOR MANUFACTURING THE SAME
Disclosed is a method for forming an image sensor device. First, a lens is provided, and a first sacrificial element is then formed on the lens. Subsequently,...
2011/0298072 RIDGE STRUCTURE FOR BACK SIDE ILLUMINATED IMAGE SENSOR
Provided is an image sensor device. The image sensor device includes a substrate having a front side and a back side. The image sensor includes first and second...
2011/0298071 HIGH POWER DENSITY BETAVOLTAIC BATTERY
To increase total power in a betavoltaic device, it is desirable to have greater radioisotope material and/or semiconductor surface area, rather than greater...
2011/0298070 Semiconductor Device Having Magnetoresistive Element and Manufacturing Method Thereof
A semiconductor device has a magnetoresistive element, a bit line over the magnetoresistive element, and a yoke cover over the bit line. To form the yoke cover,...
2011/0298069 MAGNETIC RANDOM ACCESS MEMORY WITH DUAL SPIN TORQUE REFERENCE LAYERS
A magnetic data storage cell, applicable to spin-torque random access memory (ST-RAM), is disclosed. A magnetic cell includes first and second fixed magnetic...
2011/0298068 MAGNETIC TUNNEL JUNCTION WITH COMPENSATION ELEMENT
A magnetic tunnel junction having a compsensation element is disclosed. The magnetic tunnel junction includes a reference element, and a compensation element...
2011/0298067 MAGNETIC MEMORY ELEMENT AND MAGNETIC MEMORY
A magnetoresistive effect element includes: a magnetization free layer; a non-magnetic insertion layer provided adjacent to the magnetization free layer; a...
2011/0298066 MICRO STRUCTURE, MICRO ELECTRO MECHANICAL SYSTEM THEREWITH, AND MANUFACTURING METHOD THEREOF
A micro structure includes a base member; a supporting unit disposed on a surface of the base member; a graphene unit which covers at least a portion of the...
2011/0298065 ELECTROMECHANICAL SYSTEM HAVING A CONTROLLED ATMOSPHERE, AND METHOD OF FABRICATING SAME
There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of fabricating or manufacturing MEMS...
2011/0298064 SENSOR MODULE AND METHOD FOR PRODUCING SENSOR MODULES
Sensor module, comprising a carrier, at least one sensor chip and at least one evaluation chip which is electrically coupled to the sensor chip. The carrier has...
2011/0298063 Micromechanical Component
A method is described for manufacturing a micromechanical component. The method includes providing a first substrate, forming a first connecting structure on...
2011/0298062 METAL GATE STRUCTURES AND METHODS FOR FORMING THEREOF
Metal gate structures and methods for forming thereof are provided herein. In some embodiments, a method for forming a metal gate structure on a substrate...
2011/0298061 STRUCTURE AND METHOD FOR REPLACEMENT GATE MOSFET WITH SELF-ALIGNED CONTACT USING SACRIFICIAL MANDREL DIELECTRIC
The present disclosure provides a method for forming a semiconductor device that includes forming a replacement gate structure overlying a channel region of a...
2011/0298060 INTERFACE STRUCTURE FOR CHANNEL MOBILITY IMPROVEMENT IN HIGH-K METAL GATE STACK
A gate stack structure for field effect transistor (FET) devices includes a nitrogen rich first dielectric layer formed over a semiconductor substrate surface;...
2011/0298059 INTEGRATED CIRCUITS HAVING DUMMY GATE ELECTRODES AND METHODS OF FORMING THE SAME
An integrated circuit includes at least one first gate electrode of at least one active transistor. At least one first dummy gate electrode is disposed adjacent...
2011/0298058 FACETED EPI SHAPE AND HALF-WRAP AROUND SILICIDE IN S/D MERGED FINFET
FinFETs and methods of making. FinFETs are provided. The FinFET contains two or more fins over a semiconductor substrate; two or more epitaxial layers over side...
2011/0298057 SEMICONDUCTOR DEVICE
An object is to provide a semiconductor device having a novel structure with a high degree of integration. A semiconductor device includes a semiconductor layer...
2011/0298056 CONTACT RESISTIVITY REDUCTION IN TRANSISTOR DEVICES BY DEEP LEVEL IMPURITY FORMATION
A method of forming a low resistance contact structure in a semiconductor device includes forming a doped semiconductor region in a semiconductor substrate;...
2011/0298055 Semiconductor device and manufacturing method for the same
In a semiconductor substrate on which are formed an N-type MOS transistor and a P-type MOS transistor, the gate electrode of the N-type MOS transistor comprises...
2011/0298054 One-time programmable memory
The present invention provides a programmable memory array including a plurality of memory cells. At least one and preferably each memory cell of the plurality...
2011/0298053 MANUFACTURING METHOD OF GATE STACK AND SEMICONDUCTOR DEVICE
A manufacturing method of a gate stack with sacrificial oxygen-scavenging metal spacers includes: forming a gate stack structure consisting of an interfacial...
2011/0298052 Vertical Stacking of Field Effect Transistor Structures for Logic Gates
A vertical structure is formed upon a semiconductor substrate. The vertical structure comprises four dielectric layers parallel to a top surface of the...
2011/0298051 Electrostatic Discharge Management Apparatus, Systems, and Methods
Apparatus, systems, and methods may include managing electrostatic discharge events by using a semiconductor device having a non-aligned gate to implement a...
2011/0298050 FIN TRANSISTOR STRUCTURE AND METHOD OF FABRICATING THE SAME
There is provided a fin transistor structure and a method of fabricating the same. The fin transistor structure comprises a fin formed on a semiconductor...
2011/0298049 CMOS Device with Raised Source and Drain Regions
A semiconductor structure includes a semiconductor substrate comprising a PMOS region and an NMOS region; a PMOS device in the PMOS region; and an NMOS device...
2011/0298048 SEMICONDUCTOR DEVICE
The present teaching provides a semiconductor device capable of relaxing stress transferred to a contact region during wire bonding and improving reliability of...
2011/0298047 THREE-DIMENSIONAL SEMICONDUCTOR DEVICE STRUCTURES AND METHODS
A three-dimensional semiconductor device includes a first semiconductor device, a second semiconductor device, and a patterned conductive layer disposed between...
2011/0298046 SEMICONDUCTOR DEVICE WITH BURIED BIT LINES AND METHOD FOR FABRICATING THE SAME
A semiconductor device includes active regions separated by a trench, a separation layer dividing the trench, and buried bit lines buried in the trench with the...
2011/0298045 SELF-ALIGNED CONTACT FOR TRENCH MOSFET
The process methods and structures mentioned above for creating a trench MOSFET enables self-aligned contacts to be formed to allow decreasing pitch size for...
2011/0298044 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
The semiconductor device according to the present invention includes a semiconductor layer, a trench formed by digging the semiconductor layer from the surface...
2011/0298043 Semiconductor Device Structures and Related Processes
Improved highly reliable power RFP structures and fabrication and operation processes. The structure includes plurality of localized dopant concentrated zones...
2011/0298042 POWER SEMICONDUCTOR DEVICE WITH TRENCH BOTTOM POLYSILICON AND FABRICATION METHOD THEREOF
A power semiconductor device comprising a base, a trench, a heavily doped polysilicon structure, a polysilicon gate, a gate dielectric layer, and a heavily...
2011/0298041 SINGLE-GATE FINFET AND FABRICATION METHOD THEREOF
A single-gate FinFET structure includes an active fin structure having two enlarged head portions and two respective tapered neck portions that connect the...
2011/0298040 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device and a method of manufacturing the same are disclosed. By forming a boron nitride film as a sealing film of a buried gate of a cell region...
2011/0298039 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE PROVIDED WITH CHARGE STORAGE LAYER IN MEMORY CELL
A nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a charge storage...
2011/0298038 THREE DIMENSIONAL SEMICONDUCTOR DEVICE
Provided are a three-dimensional semiconductor memory device and manufacturing method of the three-dimensional semiconductor memory device. The...
2011/0298037 VERTICAL STRUCTURE NONVOLATILE MEMORY DEVICES
A vertical structure nonvolatile memory device can include a channel layer that extends in a vertical direction on a substrate. A memory cell string includes a...
2011/0298036 ISOLATION LAYER STRUCTURE, METHOD OF FORMING THE SAME AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE...
An isolation layer structure includes first to fourth oxide layer patterns. The first and third oxide layer patterns are sequentially formed in a first trench...
2011/0298035 MEMORY DEVICE TRANSISTORS
Method and device embodiments are described for fabricating MOSFET transistors in a semiconductor also containing non-volatile floating gate transistors. MOSFET...
2011/0298034 MEMORY CELL
A non-volatile memory cell (200) comprising a floating gate transistor (206) comprising a floating gate (10) positioned between a control gate (14) and a first...
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