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| Patent # | Description |
|---|---|
| 2012/0074588 |
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH WARPAGE CONTROL AND METHOD OF
MANUFACTURE THEREOF A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit device having chip interconnects; applying an... |
| 2012/0074587 |
Semiconductor Device and Method of Bonding Different Size Semiconductor
Die at the Wafer Level A semiconductor wafer has first and second opposing surfaces. A plurality of conductive vias is formed partially through the first surface of the semiconductor... |
| 2012/0074586 |
METHODS OF FABRICATING PACKAGE STACK STRUCTURE AND METHOD OF MOUNTING
PACKAGE STACK STRUCTURE ON SYSTEM BOARD A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a... |
| 2012/0074585 |
Semiconductor Device and Method of Forming TSV Interposer With
Semiconductor Die and Build-Up Interconnect... A semiconductor device has a substrate with first and second opposing surfaces. A plurality of conductive vias is formed partially through the first surface of... |
| 2012/0074584 |
MULTI-LAYER TSV INSULATION AND METHODS OF FABRICATING THE SAME Provided is a semiconductor device. The semiconductor device may include a substrate and a stacked insulation layer on a sidewall of an opening which penetrates... |
| 2012/0074583 |
SEMICONDUCTOR STRUCTURE HAVING A THROUGH SUBSTRATE VIA (TSV) AND METHOD
FOR FORMING A structure having a substrate includes an opening in the substrate having depth from a top surface of the substrate to a bottom surface of the substrate. A... |
| 2012/0074582 |
DEVICE WITH THROUGH-SILICON VIA (TSV) AND METHOD OF FORMING THE SAME A device with through-silicon via (TSV) and a method of forming the same includes the formation of an opening in a silicon substrate, the formation of a first... |
| 2012/0074581 |
DIE-STACKING USING THROUGH-SILICON VIAS ON BUMPLESS BUILD-UP LAYER
SUBSTRATES INCLUDING EMBEDDED-DICE, AND... An apparatus includes a coreless substrate with a through-silicon via (TSV) embedded die that is integral to the coreless substrate. The apparatus includes a... |
| 2012/0074580 |
METHODS OF FORMING FULLY EMBEDDED BUMPLESS BUILD-UP LAYER PACKAGES AND
STRUCTURES FORMED THEREBY Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include a die embedded in a... |
| 2012/0074579 |
SEMICONDUCTOR CHIP WITH REINFORCING THROUGH-SILICON-VIAS A method of manufacturing includes connecting a first end of a first through-silicon-via to a first die seal proximate a first side of a first semiconductor... |
| 2012/0074578 |
SEMICONDUCTOR ELEMENT, SEMICONDUCTOR ELEMENT MOUNTED BOARD, AND METHOD OF
MANUFACTURING SEMICONDUCTOR ELEMENT A semiconductor element includes connection terminals. The connection terminals are each shaped in such a manner that the transverse cross-sectional area in a... |
| 2012/0074577 |
SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING OF SEMICONDUCTOR DEVICE,
AND SWITCHING CIRCUIT It is an objective to provide a semiconductor device with low leak current. The semiconductor device includes a plurality of ground side electrodes and a... |
| 2012/0074576 |
INTERCONNECT FOR AN OPTOELECTRONIC DEVICE Interconnects for optoelectronic devices are described. An interconnect may include a stress relief feature. An interconnect may include an L-shaped feature. |
| 2012/0074575 |
COPPER LINE HAVING SELF-ASSEMBLED MONOLAYER FOR ULSI SEMICONDUCTOR
DEVICES, AND A METHOD OF FORMING SAME A copper line having self assembled monolayer for use in ULSI semiconductor devices and methods of making the same are presented. The copper line includes an... |
| 2012/0074574 |
SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING SAME One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece;... |
| 2012/0074573 |
SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING SAME One or more embodiments relate to a method of forming a semiconductor device, comprising: forming a structure, the structure including at least a first element... |
| 2012/0074572 |
SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING SAME One or more embodiments relate to a method for making a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece;... |
| 2012/0074571 |
METHODS AND ARCHITECTURES FOR BOTTOMLESS INTERCONNECT VIAS An apparatus includes an interconnect in a recess. The interconnect includes a liner structure and the liner structure in the recess. The liner structure is... |
| 2012/0074570 |
Method for Forming a Through Via in a Semiconductor Element and
Semiconductor Element Comprising the Same A method for forming a through via in a semiconductor element includes providing a semiconductor element having electronic circuitry integrated on the main side... |
| 2012/0074569 |
SEMICONDUCTOR DEVICE A semiconductor device includes a substrate having external connection terminals, and a semiconductor chip mounted over a semiconductor-chip mounting portion of... |
| 2012/0074568 |
METHOD AND SYSTEM FOR MINIMIZING CARRIER STRESS OF A SEMICONDUCTOR DEVICE A method and a system for minimizing carrier stress of a semiconductor device are provided. In one embodiment, a semiconductor device is provided comprising a... |
| 2012/0074567 |
Semiconductor Device and Method of Forming Vertical Interconnect Structure
Between Non-Linear Portions of... A semiconductor device is made by forming a first conductive layer over a first temporary carrier having rounded indentations. The first conductive layer has a... |
| 2012/0074566 |
Package For Semiconductor Device Including Guide Rings And Manufacturing
Method Of The Same An example embodiment relates to a semiconductor package. The semiconductor package includes a first substrate including a first pad, a second substrate... |
| 2012/0074565 |
SEMICONDUCTOR DEVICE PROVIDED WITH REAR PROTECTIVE FILM ON OTHER SIDE OF
SEMICONDUCTOR SUBSTRATE AND... An opening is formed in a part of a rear protective film corresponding to the center of a dicing street by laser processing which applies a laser beam. The rear... |
| 2012/0074564 |
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME A semiconductor device comprises a semiconductor substrate having a connection pad, an external connection electrode provided on the semiconductor substrate to... |
| 2012/0074563 |
Semiconductor apparatus and the method of manufacturing the same A semiconductor apparatus includes a semiconductor chip, a post electrode positioned on the front surface electrode, and a metal particle layer having metal... |
| 2012/0074562 |
Three-Dimensional Integrated Circuit Structure with Low-K Materials A device includes an interposer free from active devices therein. The interposer includes a substrate; a through-substrate via (TSV) penetrating through the... |
| 2012/0074561 |
BACKMETAL REPLACEMENT FOR USE IN THE PACKAGING OF INTEGRATED CIRCUITS One aspect of the invention pertains to an arrangement for forming exposed die packages. The arrangement includes a semiconductor wafer having multiple... |
| 2012/0074560 |
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH WARPAGE CONTROL AND METHOD OF
MANUFACTURE THEREOF A method of manufacture of an integrated circuit packaging system includes: providing a carrier; mounting an integrated circuit device having component... |
| 2012/0074559 |
INTEGRATED CIRCUIT PACKAGE USING THROUGH SUBSTRATE VIAS TO GROUND LID An integrated circuit package including a package substrate, a metal lid mounted to the package substrate, and a stack of two or more integrated circuit chips... |
| 2012/0074558 |
Circuit Board Packaged with Die through Surface Mount Technology A package of a circuit board and a die are packed through surface mount technology (SMT). The shortest circuit is formed with at a low cost. Thus, the package... |
| 2012/0074557 |
Integrated Circuit Package Lid Configured For Package Coplanarity An integrated circuit package apparatus comprises a packaging substrate, an integrated circuit coupled to an upper side of the packaging substrate, an array of... |
| 2012/0074556 |
SEMICONDUCTOR POWER MODULE AND METHOD OF MANUFACTURING THE SAME A semiconductor power module according to the present invention includes a base member, a semiconductor power device having a surface and a rear surface with... |
| 2012/0074555 |
SEMICONDUCTOR PACKAGE INCLUDING CAP A semiconductor package comprises: a substrate comprising a semiconductor device; a cap comprising a seal ring disposed over a surface of the cap; and a gap... |
| 2012/0074554 |
BOND RING FOR A FIRST AND SECOND SUBSTRATE The present disclosure provides a device having a plurality of bonded substrates. The substrates are bonded by a first bond ring and a second bond ring. In an... |
| 2012/0074553 |
METHOD AND SYSTEM FOR IMPROVING RELIABILITY OF A SEMICONDUCTOR DEVICE A method and a system for improving reliability of a semiconductor device are provided. In one embodiment, a semiconductor device is provided comprising a... |
| 2012/0074552 |
CIRCUIT DEVICE AND METHOD FOR MANUFACTURING THE SAME In a hybrid integrated circuit device, a circuit board on which an island portion of a lead is fixedly attached and a control board on which a control element... |
| 2012/0074551 |
SEMICONDUCTOR DEVICE An improved reliability of a junction region between a bonding wire and an electrode pad in an operation at higher temperature is presented. A semiconductor... |
| 2012/0074550 |
LEAD FRAME, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING
SEMICONDUCTOR DEVICE A lead frame includes a die stage; an inner lead provided near the die stage; and a bus bar provided between the die stage and the inner lead and supported by a... |
| 2012/0074549 |
SEMICONDUCTOR DEVICE WITH EXPOSED PAD A semiconductor device has a die attached to a die pad and electrically connected to lead fingers. The die, a top surface of the die pad, and a first portion of... |
| 2012/0074548 |
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERLOCK AND METHOD OF
MANUFACTURE THEREOF A method of manufacture of an integrated circuit packaging system includes: forming a package paddle; forming a lead adjacent the package paddle, the lead... |
| 2012/0074547 |
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD ENCAPSULATION AND METHOD OF
MANUFACTURE THEREOF A method of manufacture of an integrated circuit packaging system includes: forming a package paddle; forming a lead adjacent the package paddle, the lead... |
| 2012/0074546 |
Multi-chip Semiconductor Packages and Assembly Thereof Semiconductor packages and method of fabricating them are described. In one embodiment, the semiconductor package includes a substrate having a first and a... |
| 2012/0074545 |
THIN FLIP CHIP PACKAGE STRUCTURE A thin flip chip package structure comprises a substrate, a chip and a heat dissipation paste, wherein the substrate comprises an insulating layer and a trace... |
| 2012/0074544 |
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR A semiconductor device includes, a lead frame having a die pad and a plurality of leads each disposed around the die pad, a semiconductor element rested on the... |
| 2012/0074543 |
PACKAGE APPARATUS OF POWER SEMICONDUCTOR DEVICE A package apparatus is for packaging a power semiconductor device that includes a substrate formed, a mold part molded on the substrate, and electrode terminals... |
| 2012/0074542 |
SEMICONDUCTOR DEVICE A semiconductor device, in which a control circuit board is mountable outside a sheath case and a power semiconductor element is placeable inside the sheath... |
| 2012/0074541 |
SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME A technique is provided which allows a chip mounted by wire bonding and a chip mounted by bump electrodes to share a manufacturing process. Both in a case where... |
| 2012/0074540 |
SEMICONDUCTOR CHIP PACKAGE A structure of a semiconductor chip package is provided. The semiconductor chip package includes: a substrate; a semiconductor chip mounted on a first surface... |
| 2012/0074539 |
DEVICE AND METHODS FOR ELECTROSTATIC DISCHARGE PROTECTION An ESD device includes a first and second well regions disposed in a semiconductor substrate. The first well region comprises a plurality of N wells spaced at a... |
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