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Patent # Description
2016/0099365 Collector grid and interconnect structures for photovoltaic arrays and modules
An interconnected arrangement of photovoltaic cells is achieved using laminating current collector electrodes. The electrodes comprise a pattern of conductive...
2016/0099364 METHOD FOR FORMING DENDRITIC SILVER WITH PERIODIC STRUCTURE AS LIGHHT-TRAPPING LAYER
The invention is related to a method for forming dendritic silver with periodic structure as light-trapping layer, includes these steps: form a photoresist...
2016/0099363 USING SOLAR CELLS AS BYPASS DIODE HEAT SINKS
A solar panel includes a plurality of solar cells, a bypass diode unit, and a heat spreader. The bypass diode unit includes a bypass diode coupled in an...
2016/0099362 System and Method for Deploying Radiation Energy Conversion Cells
A radiation energy conversion system comprises: an environmental barrier cover having a barrier cover inner surface; an environmental barrier enclosure...
2016/0099361 ELEMENT AND PHOTOVOLTAIC CELL
The invention provides an element including a semiconductor substrate and an electrode disposed on the semiconductor substrate, the electrode being a sintered...
2016/0099360 WAFER FOR SOLAR CELL, METHOD OF PRODUCING WAFER FOR SOLAR CELL, METHOD OF PRODUCING SOLAR CELL, AND METHOD OF...
Provided is a wafer for solar cell which can be produced using a polycrystalline semiconductor wafer cut out using a bonded abrasive wire, which wafer can be...
2016/0099359 SOLAR PANEL AND METHOD FOR MANUFACTURING SUCH A SOLAR PANEL
A solar panel is provided with a stack including at least one back contacted solar cell and a back-sheet layer. The back-sheet layer has a patterned conductive...
2016/0099358 Method of Manufacturing Semiconductor Device
A semiconductor device including a nonvolatile memory cell and a field effect transistor together is improved in performance. In a method of manufacturing a...
2016/0099357 THIN FILM TRANSISTOR
Provided is a thin film transistor having an oxide semiconductor layer that has high mobility, excellent stress resistance, and good wet etching property. The...
2016/0099356 SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE
A multi-gate structure is used and a width (d1) of a high concentration impurity region sandwiched by two channel forming regions in a channel length direction...
2016/0099355 NON-VOLATILE MEMORY DEVICES WITH THIN-FILM AND MONO-CRYSTALLINE SILICON TRANSISTORS
A non-volatile memory device combines thin-film transistor-based memory cells with bulk mono-crystalline silicon transistors, which can more efficiently drive...
2016/0099354 Recessed Transistors Containing Ferroelectric Material
Some embodiments include transistor constructions having a first insulative structure lining a recess within a base. A first conductive structure lines an...
2016/0099353 SEMICONDUCTOR DEVICE
A semiconductor device in which release of oxygen from side surfaces of an oxide semiconductor film including c-axis aligned crystal parts can be prevented is...
2016/0099352 FETS AND METHODS OF FORMING FETS
An embodiment is a structure. The structure comprises a fin on a substrate, isolation regions on the substrate, a dielectric region, and a gate structure. The...
2016/0099351 SELF-ALIGNED SLOTTED ACCUMULATION-MODE FIELD EFFECT TRANSISTOR (ACCUFET) STRUCTURE AND METHOD
This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having...
2016/0099350 SEMICONDUCTOR DEVICE
A semiconductor device includes a fin-shaped semiconductor layer on a semiconductor substrate and extends in a first direction with a first insulating film...
2016/0099349 SEMICONDUCTOR DEVICE WITH NON-ISOLATED POWER TRANSISTOR WITH INTEGRATED DIODE PROTECTION
A semiconductor device configured with one or more integrated breakdown protection diodes in non-isolated power transistor devices and electronic apparatus,...
2016/0099348 HIGH VOLTAGE DOUBLE-DIFFUSED MOS (DMOS) DEVICE AND METHOD OF MANUFACTURE
A method of forming an integrated DMOS transistor/EEPROM cell includes forming a first mask over a substrate, forming a drift implant in the substrate using...
2016/0099347 LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
Provided is a manufacturing method for a laterally diffused metal oxide semiconductor device, comprising the following steps: growing an oxide layer on a...
2016/0099346 SEMICONDUCTOR DEVICE
A semiconductor device including a gate structure, a source region, a drain region, a first conductive type epitaxial layer, a high voltage second conductive...
2016/0099345 High Electron Mobility Transistor with Periodically Carbon Doped Gallium Nitride
A method for forming a high electron mobility transistor (HEMT) device with a plurality of alternating layers of one or more undoped gallium nitride (GaN)...
2016/0099344 FACILITATING FABRICATING GATE-ALL-AROUND NANOWIRE FIELD-EFFECT TRANSISTORS
Methods are presented for facilitating fabrication of a semiconductor device, such as a gate-all-around nanowire field-effect transistor. The methods include,...
2016/0099343 TUNNELING FIELD EFFECT TRANSISTOR AND METHODS OF MAKING SUCH A TRANSISTOR
One illustrative method of forming a TFET device includes forming a first semiconductor material that extends for a full length of a drain region, a gate...
2016/0099342 STRUCTURE AND METHOD TO INCREASE CONTACT AREA IN UNMERGED EPI INTEGRATION FOR CMOS FINFETS
Source/drain contact structures with increased contact areas for a multiple fin-based complementary metal oxide semiconductor field effect transistor (CMOSFET)...
2016/0099341 HIGH BREAKDOWN VOLTAGE LDMOS DEVICE
A multi-region (81, 83) lateral-diffused-metal-oxide-semiconductor (LDMOS) device (40) has a semiconductor-on-insulator (SOI) support structure (21) on or over...
2016/0099340 HIGH VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE AND METHOD OF FORMING THE SAME
A HVMOS transistor device is provided. The HVMOS has a substrate, a gate structure, a drain region and a source region, a base region and a gate dielectric...
2016/0099339 NOVEL EMBEDDED SHAPE SIGE FOR STRAINED CHANNEL TRANSISTORS
An integrated circuit die includes a silicon substrate. PMOS and NMOS transistors are formed on the silicon substrate. The carrier mobilities of the PMOS and...
2016/0099338 STACKED PLANAR DOUBLE-GATE LAMELLAR FIELD-EFFECT TRANSISTOR
A method of making a field-effect transistor device includes providing a substrate with a fin stack having: a first sacrificial material layer on the...
2016/0099337 GATE STRUCTURE HAVING DESIGNED PROFILE AND METHOD FOR FORMING THE SAME
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a metal gate structure having curved sidewalls...
2016/0099336 OPC ENLARGED DUMMY ELECTRODE TO ELIMINATE SKI SLOPE AT ESIGE
Enlarging the dummy electrode to the STI top width size by OPC cut mask correction and the resulting device are disclosed. Embodiments include forming an STI...
2016/0099335 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes: a first electrode; a second electrode; an interlayer insulating film made of a porous insulating material and formed above the...
2016/0099334 BIPOLAR TRANSISTOR MANUFACTURING METHOD
A method for manufacturing a bipolar transistor, including the steps of: forming a first surface-doped region of a semiconductor substrate having a...
2016/0099333 FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATION
An improved field effect transistor and method of fabrication are disclosed. A barrier layer stack is formed in the base and sidewalls of a gate cavity. The...
2016/0099332 PARTIAL SACRIFICIAL DUMMY GATE WITH CMOS DEVICE WITH HIGH-K METAL GATE
A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections, a bottom portion, a top portion, and a sacrificial...
2016/0099331 Self-Aligned Dual-Metal Silicide and Germanide Formation
A device having an epitaxial region and dual metal-semiconductor alloy surfaces is provided. The epitaxial region includes an upward facing facet and a...
2016/0099330 SEMICONDUCTOR DEVICE WITH NANOWIRES IN DIFFERENT REGIONS AT DIFFERENT HEIGHTS
A semiconductor device has gate-all-around devices formed in respective regions on a substrate. The gate-all-around devices have nanowires at different levels....
2016/0099329 SUSPENDED BODY FIELD EFFECT TRANSISTOR
A semiconductor fin including a vertical stack, from bottom to top, of a second semiconductor material and a first semiconductor material is formed on a...
2016/0099328 METHOD OF FORMING NANOWIRES
According to another embodiment, a semiconductor structure is provided. The structure includes: a substrate; a first nanowire over the substrate; and a second...
2016/0099327 THIN FILM TRANSISTOR ARRAY PANEL
A thin film transistor array panel is capable of increasing an aperture ratio and decreasing parasitic capacitance between a gate electrode and a drain...
2016/0099326 METHOD FOR MAKING AN INTEGRATED CIRCUIT
A method includes making a gate stack on the surface of an active zone, including depositing a first dielectric layer; depositing a gate conductive layer;...
2016/0099325 DUAL OXIDE TRENCH GATE POWER MOSFET USING OXIDE FILLED TRENCH
A power MOSFET device including a semiconductor layer, an active trench formed in the semiconductor layer and housing a dual oxide thickness trench gate...
2016/0099324 STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH GATE STACK
A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a first gate...
2016/0099323 SEMICONDUCTOR STRUCTURES AND METHODS OF FABRICATION OF SAME
Methods of fabricating a semiconductor structure comprise forming an opening through a stack of alternating tier dielectric materials and tier control gate...
2016/0099322 SEMICONDUCTOR DEVICES WITH SIDEWALL SPACERS OF EQUAL THICKNESS
Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a...
2016/0099321 SEMICONDUCTOR DEVICE COMPRISING CONTACT STRUCTURES WITH PROTECTION LAYERS FORMED ON SIDEWALLS OF CONTACT ETCH...
A semiconductor device includes a silicide contact region positioned at least partially in a semiconductor layer, an etch stop layer positioned above the...
2016/0099320 SEMICONDUCTOR COMPOSITE FILM WITH HETEROJUNCTION AND MANUFACTURING METHOD THEREOF
The present invention discloses a semiconductor composite film with a heterojunction and a manufacturing method thereof. The semiconductor composite film...
2016/0099319 SEMICONDUCTOR WAFER INCLUDING A MONOCRYSTALLINE SEMICONDUCTOR LAYER SPACED APART FROM A POLY TEMPLATE LAYER
A semiconductor wafer can include a substrate, a poly template layer, and a semiconductor layer. The substrate has a central region and an edge region, the...
2016/0099318 STRUCTURE AND METHOD FOR TRANSIENT VOLTAGE SUPPRESSION DEVICES WITH A TWO-REGION BASE
A transient voltage suppression (TVS) device and a method of forming the device are provided. The TVS device includes a first layer of wide band-gap...
2016/0099317 VERTICAL SEMICONDUCTOR DEVICES INCLUDING SUPERLATTICE PUNCH THROUGH STOP LAYER AND RELATED METHODS
A semiconductor device may include a substrate, and a plurality of fins spaced apart on the substrate. Each of the fins may include a lower semiconductor fin...
2016/0099316 Semiconductor Device and Manufacturing Method Thereof
In a silicon carbide semiconductor device having a trench type MOS gate structure, the present invention makes it possible to inhibit the operating...
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