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Patent # Description
2016/0099265 DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME
A display apparatus includes a base substrate, a pixel on the base substrate, and a color filter part between the base substrate and the pixel. The pixel...
2016/0099264 SYSTEM AND METHOD OF MANUFACTURING A THIN FILM TRANSISTOR SUBSTRATE
In a method of manufacturing a thin film transistor substrate, a first metal layer is formed on a first surface of a base substrate. The base substrate is...
2016/0099263 DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME
Provided are a display device and a method of manufacturing of the display device. The display device includes a substrate subjected to a primary preprocess; a...
2016/0099262 Hybrid Pixel Control Circuits for Light-Emitting Diode Display
An electronic device may include a display. The display may be formed by an array of light-emitting diodes mounted to the surface of a substrate. The...
2016/0099261 Metal Wiring and Method of Manufacturing the Same, and Metal Wiring Substrate and Method of Manufacturing the Same
A metal wiring suitable for a substrate of large size is provided. The present invention is characterized in that at least one layer of conductive film is...
2016/0099260 DISPLAY PANEL
A display panel includes a substrate, a plurality of first signal lines, a plurality of second signal lines, a plurality of pixel units, a plurality of...
2016/0099259 Wiring Layer and Manufacturing Method Therefor
To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a...
2016/0099258 SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE
To provide a novel semiconductor device or a semiconductor device capable of operating at high speed. The semiconductor device includes a plurality of circuits...
2016/0099257 THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
A thin film transistor includes an active pattern formed on a substrate; a gate pattern formed on the active pattern and comprising a gate electrode and a gate...
2016/0099256 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME
According to one embodiment, a semiconductor memory device includes a substrate; a memory cell array including a plurality of memory cells and stacked on the...
2016/0099255 THREE DIMENSIONAL STACKED SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
A 3D stacked semiconductor structure is provided, comprising a plurality of multi-layered pillars formed on a substrate and spaced apart from each other, a...
2016/0099254 Memory Hole Structure in Three Dimensional Memory
In a three dimensional nonvolatile memory, memory holes extend vertically through two or more physical levels in which memory cells are formed. Memory hole...
2016/0099253 METHOD OF INTEGRATING A CHARGE-TRAPPING GATE STACK INTO A CMOS FLOW
A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a...
2016/0099252 MEMORY HAVING A CONTINUOUS CHANNEL
The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical...
2016/0099251 SEMICONDUCTOR DEVICE
An insulating film, which is sandwiched between a gate electrode formed on an SOI layer constituting an SOI substrate and an epitaxial layer formed on the SOI...
2016/0099250 THREE DIMENSIONAL NAND DEVICE WITH SILICON GERMANIUM HETEROSTRUCTURE CHANNEL
A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of a first material and a second material...
2016/0099249 INTEGRATED FIN AND STRAP STRUCTURE FOR AN ACCESS TRANSISTOR OF A TRENCH CAPACITOR
At least one dielectric pad layer is formed on a semiconductor-on-insulator (SOI) substrate. A deep trench is formed in the SOI substrate, and a combination of...
2016/0099248 SEMICONDUCTOR MEMORY DEVICE WITH IMPROVED ACTIVE AREA/WORD LINE LAYOUT
One semiconductor device includes a bit line extending in a straight line in an X direction, a first and a second horizontal active region extending in the X...
2016/0099247 SEMICONDUCTOR DEVICES WITH CAPACITORS
A semiconductor device includes bottom electrodes two-dimensionally arranged on a substrate and transistors connected to the bottom electrodes, respectively....
2016/0099246 STRUCTURE AND METHOD TO INCREASE CONTACT AREA IN UNMERGED EPI INTEGRATION FOR CMOS FINFETS
Source/drain contact structures with increased contact areas for a multiple fin-based complementary metal oxide semiconductor field effect transistor (CMOSFET)...
2016/0099245 SEMICONDUCTOR DEVICES WITH SIDEWALL SPACERS OF EQUAL THICKNESS
Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a...
2016/0099244 Methods of Forming Semiconductor Devices and Structures Thereof
Methods of forming semiconductor devices and structures thereof are disclosed. In some embodiments, a semiconductor device includes a substrate that includes...
2016/0099243 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device, and a method of manufacturing the same, includes first and second gate structures extending in a first direction and spaced apart from...
2016/0099242 SEMICONDUCTOR DEVICE EMPLOYING TRENCHES FOR ACTIVE GATE AND ISOLATION
A semiconductor device includes a semiconductor layer of a first conductivity type formed on a substrate; a first trench formed in the semiconductor layer...
2016/0099241 N-TYPE METAL OXIDE SEMICONDUCTOR (NMOS) TRANSISTOR FOR ELECTROSTATIC DISCHARGE (ESD)
One or more techniques or systems for forming an n-type metal oxide semiconductor (NMOS) transistor for electrostatic discharge (ESD) are provided herein. In...
2016/0099240 INTEGRATED ELECTROSTATIC DISCHARGE (ESD) CLAMPING
A method of fabricating a laterally diffused metal-oxide-semiconductor (LDMOS) transistor device having a bipolar transistor for electrostatic discharge (ESD)...
2016/0099239 METHODS, APPARATUS AND SYSTEM FOR REDUCTION OF POWER CONSUMPTION IN A SEMICONDUCTOR DEVICE
At least one method, apparatus and system disclosed herein involves performing power reduction process on a FinFET device. A first design is provided. The...
2016/0099238 EMBEDDED PACKAGE AND METHOD THEREOF
The present invention discloses anew embedded package comprising: a pre-mold lead frame with a plurality of chips attached thereon, where the molding material...
2016/0099237 MICROELECTRONIC DIE PACKAGES WITH METAL LEADS, INCLUDING METAL LEADS FOR STACKED DIE PACKAGES, AND ASSOCIATED...
Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked...
2016/0099236 LIGHT EMITTING LAMP
Disclosed is a light emitting lamp including a light source module including at least one light source and a light guide layer disposed on a substrate burying...
2016/0099235 METHOD OF MANUFACTURING A SINGLE LIGHT-EMITTING STRUCTURE
The instant disclosure provides a light-emitting module and a method of manufacturing a single light-emitting structure. The light-emitting module includes two...
2016/0099234 USING INTERRUPTED THROUGH-SILICON-VIAS IN INTEGRATED CIRCUITS ADAPTED FOR STACKING
In an integrated circuit (IC) adapted for use in a stack of interconnected ICs, interrupted through-silicon-vias (TSVs) are provided in addition to...
2016/0099233 HETEROGENEOUS ANNEALING METHOD AND DEVICE
A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having...
2016/0099232 FINGERPRINT RECOGNITION SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
A fingerprint recognition semiconductor device includes an insulation layer, a wiring pattern formed on a lower surface of the insulation layer, and a sensor...
2016/0099231 SEMICONDUCTOR PACKAGE ASSEMBLY
The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package and a second semiconductor...
2016/0099230 MULTI-CHIP PACKAGE, TEST SYSTEM AND METHOD OF OPERATING THE SAME
A multi-chip package includes: a plurality of semiconductor chips that are coupled with each other through normal through silicon vias and repair through...
2016/0099229 SEMICONDUCTOR DEVICES HAVING THROUGH ELECTRODES, SEMICONDUCTOR PACKAGES INCLUDING THE SAME, METHODS OF...
A semiconductor device includes a substrate having a first surface and a second surface that are opposite to each other, a plurality of through electrodes...
2016/0099228 METHOD AND APPARATUS FOR DIE-TO-DIE PAD CONTACT
A semiconductor device includes at least a first semiconductor die and a second semiconductor die. The first semiconductor dies comprises a first and second...
2016/0099227 FLEXIBLE INTERCONNECTS FOR MODULES OF INTEGRATED CIRCUITS AND METHODS OF MAKING AND USING THE SAME
Flexible interconnects, flexible integrated circuit systems and devices, and methods of making and using flexible integrated circuitry are presented herein. A...
2016/0099226 CIRCUIT SUBSTRATE INTERCONNECT
A packaged integrated circuit (IC) includes a substrate including a first substrate pad disposed on a first side of the substrate, an IC die disposed on the...
2016/0099225 Die Bonder and Bonding Method
A die bonder and a bonding method are provided that are capable of surely mounting a die on an intermediate stage and surely picking up the die from the...
2016/0099224 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device according to the present invention includes an insulating substrate having a circuit pattern, semiconductor elements bonded on the...
2016/0099223 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A method of manufacturing a semiconductor structure includes receiving a substrate including a die pad disposed thereon; disposing a passivation over the...
2016/0099222 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH UNDER BUMP METALLIZATION AND METHOD OF MANUFACTURE THEREOF
An integrated circuit packaging system and method of manufacture thereof including: providing a substrate; forming contact pads on top of the substrate;...
2016/0099221 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure includes a semiconductive substrate, a post passivation interconnect (PPI) and a polymer layer. The PPI is disposed above the...
2016/0099220 HIGH ISOLATION WIDEBAND SWITCH
A high isolation wideband switch is disclosed. In one aspect, the switch includes an integrated circuit package having an integrated circuit die with a first...
2016/0099219 Semiconductor Device Having Features to Prevent Reverse Engineering
It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that...
2016/0099218 SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
Provided is a method of manufacturing a semiconductor package. The method includes mounting a semiconductor device on a substrate; disposing a mold on the...
2016/0099217 LINE LAYOUT AND METHOD OF SPACER SELF-ALIGNED QUADRUPLE PATTERNING FOR THE SAME
A line layout and a spacer self-aligned quadruple patterning method thereof are provided. The line layout includes a first line, a second line, a third line,...
2016/0099216 SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure...
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