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Patent # Description
2016/0099215 METHOD FOR MANUFACTURING DEVICE EMBEDDED SUBSTRATE, AND DEVICE EMBEDDED SUBSTRATE
In a method for manufacturing a device embedded substrate, a conductive via that penetrates a first insulating layer and a second insulating layer from an...
2016/0099214 FLEXIBLE ELECTRONIC CIRCUITS WITH EMBEDDED INTEGRATED CIRCUIT DIE AND METHODS OF MAKING AND USING THE SAME
Flexible integrated circuit (IC) modules, flexible IC devices, and methods of making and using flexible IC modules are presented herein. A flexible integrated...
2016/0099213 SEMICONDUCTOR PACKAGE
A semiconductor package includes a package substrate with a cavity, a plurality of semiconductor chips vertically stacked in the cavity, a first insulating...
2016/0099212 Through Package Circuit in Fan-Out Wafer Level Package
A method and apparatus are provided for manufacturing a packaged electronic device (3) having pre-formed and placed through package circuit devices (35) which...
2016/0099211 SYSTEM ON CHIP
Systems on chips are provided. A system on chip (SoC) includes a first gate line, a second gate line and a third gate line extending in a first direction, a...
2016/0099210 SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
Disclosed herein are a semiconductor package and a method of manufacturing the same, which allows a conductive path to be provided to connect upper and lower...
2016/0099209 MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
A memory device includes a substrate, first and second wirings above the substrate, a third wiring above the first and second wirings, a fourth wiring above...
2016/0099208 STACKED CONDUCTOR STRUCTURE AND METHODS FOR MANUFACTURE OF SAME
A circuit structure that includes a plurality of stacked conductor layers separated from each other by respective dielectric layers. The conductor layers may...
2016/0099207 Electronic Module Comprising a Plurality of Encapsulation Layers and a Method for Producing It
An electronic module includes a first insulation layer, at least one carrier having a first main surface, a second main surface situated opposite the first...
2016/0099206 WAFER LEVEL PACKAGING OF ELECTRONIC DEVICE
Wafer level packaged semiconductor device with enhanced heat dissipation properties. The semiconductor device includes a top and a bottom face and at least one...
2016/0099205 PACKAGE ON PACKAGE AND COMPUTING DEVICE INCLUDING THE SAME
A semiconductor package includes a printed circuit board (PCB), a chip bonded to the PCB, a mold protecting the chip and exposing a backside surface of the...
2016/0099204 PACKAGE SUBSTRATE, PACKAGE STRUCTURE, AND METHODS OF FABRICATING THE SAME
A package structure is provided, including: a board having a plurality of conductive traces; a plurality of conductive pads formed on the board and each having...
2016/0099203 SEMICONDUCTOR STACK PACKAGES
A semiconductor stack package includes a printed circuit board (PCB), a first semiconductor chip, and a second semiconductor chip. The first and second...
2016/0099202 SEMICONDUCTOR PACKAGING STRUCTURE
A semiconductor packaging structure including a circuit board, a chip, and a paste is provided. The circuit board includes a base layer, a first circuit layer,...
2016/0099201 INTEGRATED CIRCUIT DEVICES HAVING THROUGH-SILICON VIAS AND METHODS OF MANUFACTURING SUCH DEVICES
An integrated circuit device includes a semiconductor structure, a through-silicon-via (TSV) structure that penetrates through the semiconductor structure and...
2016/0099200 ALUMINUM ALLOY LEAD FRAME FOR A SEMICONDUCTOR DEVICE AND CORRESPONDING MANUFACTURING PROCESS
Described herein is a semiconductor device provided with: a die of semiconductor material; a lead frame, defining a support plate, which is designed to carry...
2016/0099199 ELECTRONIC DEVICES WITH SOLDERABLE DIE STRUCTURES AND METHODS OF FORMATION OF SUCH DEVICES
An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a...
2016/0099198 SEMICONDUCTOR PACKAGE APPARATUS
A semiconductor package apparatus includes a lead frame, a first semiconductor chip, a second semiconductor chip, a first connecting element, and a second...
2016/0099197 SEMICONDUCTOR PACKAGE AND CIRCUIT SUBSTRATE FOR THE SEMICONDUCTOR PACKAGE
Provided is a circuit substrate for a semiconductor package used for mounting a plurality of semiconductor devices. The circuit substrate including: a first...
2016/0099196 Formation of Through Via Before Contact Processing
The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process...
2016/0099195 CHIP PACKAGE AND METHOD FOR FORMING THE SAME
A chip package including a first substrate having an upper surface, a lower surface and a sidewall is provided. A sensing region or device region and a...
2016/0099194 SEMICONDUCTOR MODULE AND ELECTRICALLY-DRIVEN VEHICLE
A semiconductor module includes a first semiconductor element, a second semiconductor element, a first heat spreader electrically and thermally connected to...
2016/0099193 SEMICONDUCTOR DEVICE
A semiconductor device includes: a semiconductor substrate having a main plane; a semiconductor element provided on the main plane of the semiconductor...
2016/0099192 DUAL-SIDED RADIO-FREQUENCY PACKAGE HAVING BALL GRID ARRAY
Dual-sided radio-frequency package having ball grid array. In some embodiments, a packaged radio-frequency (RF) device may include a packaging substrate...
2016/0099191 Package-on-Package with Via on Pad Connections
An interposer includes a core dielectric material, a conductive pipe penetrating through the core dielectric material, and a metal pad underlying the...
2016/0099190 UNDERFILL MATERIAL INCLUDING BLOCK COPOLYMER TO TUNE COEFFICIENT OF THERMAL EXPANSION AND TENSILE MODULUS
Embodiments of the present disclosure are directed toward underfill material including block copolymer. In one embodiment, an underfill material includes epoxy...
2016/0099189 Semiconductor Packages and Modules with Integrated Ferrite Material
A semiconductor package includes a lead frame having a die paddle and a plurality of leads including a gate lead spaced apart from the die paddle. The...
2016/0099188 Semiconductor Device with Sensor Potential in the Active Region
A semiconductor device includes semiconductor body region and a surface region, the semiconductor body region including a first conductivity type first...
2016/0099187 3D NAND STAIRCASE CD CONTROL BY USING INTERFEROMETRIC ENDPOINT DETECTION
Embodiments of the present disclosure provide methods for forming stair-like structures in manufacturing three dimensional (3D) stacking of semiconductor...
2016/0099186 METHOD FOR POSTDOPING A SEMICONDUCTOR WAFER
A method for treating a semiconductor wafer having a basic doping is disclosed. The method includes determining a doping concentration of the basic doping, and...
2016/0099185 METHOD OF CONTROLLING AN ETCHING PROCESS FOR FORMING FINE PATTERNS OF A SEMICONDUCTOR DEVICE
A method of controlling an etching process for forming fine patterns of a semiconductor device includes forming a lower pattern having a plurality of openings...
2016/0099184 SEMICONDUCTOR CHIP AND METHOD OF ESTIMATING CAPABILITY OF SEMICONDUCTOR MANUFACTURING SYSTEM
A method of estimating the capability of a semiconductor manufacturing system is provided. Plural first transistors are formed and a first VtMM value and a...
2016/0099183 METHOD FOR RELAXING THE TRANSVERSE MECHANICAL STRESSES WITHIN THE ACTIVE REGION OF A MOS TRANSISTOR, AND...
The transverse mechanical stress within the active region of a MOS transistor is relaxed by forming an insulating incursion, such as an insulated trench,...
2016/0099182 Backside Contacts for Integrated Circuit Devices
A chip includes a semiconductor substrate, a well region in the semiconductor substrate, and a transistor formed at a front side of the semiconductor...
2016/0099181 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device comprises a substrate, a semiconductor fin, a first isolation structure and a first dummy structure. The semiconductor fin comprises a...
2016/0099180 Method for Manufacturing a Semiconductor Switching Device with Different Local Cell Geometry
A method for manufacturing a semiconductor device includes providing a semiconductor substrate having an outer rim, an active area, and an edge termination...
2016/0099179 METHOD OF FORMING SEMICONDUCTOR DEVICE
A method of forming a semiconductor device is disclosed. A substrate having multiple fins is provided. An insulating layer fills a lower portion of a gap...
2016/0099178 FIN STRUCTURE FORMATION BY SELECTIVE ETCHING
Methods and apparatus for forming FinFET structures are provided. Selective etching and deposition processes described herein may provide for FinFET...
2016/0099177 METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE
In a method, an isolation layer pattern is formed on a substrate to define first and second active fins. An ARC layer is formed on the isolation layer pattern...
2016/0099176 METHOD FOR MANUFACTURING SEMICONDUCTOR CHIP
A method for manufacturing a semiconductor chip includes forming a front-side groove in a front surface of a substrate; forming a back-side groove wider than...
2016/0099175 SEMICONDUCTOR STRUCTURE INCLUDING A THROUGH ELECTRODE, AND METHOD FOR FORMING THE SAME
A semiconductor structure including a through electrode includes a lamination body including at least three layers, including respective vertically aligned...
2016/0099174 METHOD OF FORMING AN INTERCONNECT STRUCTURE FOR A SEMICONDUCTOR DEVICE
Methods of semiconductor device fabrication are provided including those that provide a substrate having a plurality of trenches disposed in a dielectric layer...
2016/0099173 METHODS FOR ETCHING A BARRIER LAYER FOR AN INTERCONNECTION STRUCTURE FOR SEMICONDUCTOR APPLICATIONS
Embodiments of the present disclosure provide methods for etching a barrier layer disposed under a metal layer, such as a copper layer, when the metal layer is...
2016/0099172 LOW-K INTERCONNECT STRUCTURE AND FORMING METHOD THEREOF
A method of forming low-k interconnect structure is disclosed, which comprises: providing at least one protruding structure on a substrate traversing between a...
2016/0099171 DIMENSION-CONTROLLED VIA FORMATION PROCESSING
Methods are provided for dimension-controlled via formation over a circuit structure, including over multiple adjacent conductive structures. The method(s)...
2016/0099170 METHODS OF FORMING A STACK OF ELECTRODES AND THREE-DIMENSIONAL SEMICONDUCTOR DEVICES FABRICATED THEREBY
Provided are methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby. The device may include electrodes...
2016/0099169 MECHANISMS FOR FORMING RADIO FREQUENCY (RF) AREA OF INTEGRATED CIRCUIT STRUCTURE
The methods for forming a radio frequency area of an integrated circuit are provided. The method includes forming a buried oxide layer over a substrate, and an...
2016/0099168 METHOD FOR DEFINING AN ISOLATION REGION(S) OF A SEMICONDUCTOR STRUCTURE
Methods for defining an isolation region of a semiconductor structure are provided. The method includes, for instance: providing a semiconductor structure with...
2016/0099167 AIR-GAP STRUCTURE FORMATION WITH ULTRA LOW-K DIELECTRIC LAYER ON PECVD LOW-K CHAMBER
Methods for reducing the k value of a layer using air gaps and devices produced by said methods are disclosed herein. Methods disclosed herein can include...
2016/0099166 Spring-Loaded Pins For Susceptor Assembly and Processing Methods Using Same
Apparatus and methods for processing a semiconductor wafer including a susceptor assembly with recesses comprising at least three lift pins. The lift pins...
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