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LATCH INITIALIZATION FOR A DATA STORAGE DEVICE
A data storage device may include a memory die. The memory die includes a memory and a latch. A method may include receiving a command corresponding to a write...
NON-VOLATILE SEMICONDUCTOR MEMORY WITH HIGH RELIABILITY AND DATA ERASING
A non-volatile semiconductor memory apparatus and a data erasing method thereof are provided to suppress deterioration in reliability due to data rewriting. An...
A semiconductor device includes memory strings each including a drain select transistor, memory cells and a source select transistor, which are connected...
DATA WRITING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT
A data writing method, a memory storage device, and a memory control circuit unit are provided. The method includes: writing data into at least one first...
FAST SECURE ERASE IN A FLASH SYSTEM
A flash memory controller is configured to provide a first erase mode for erasing one or more groups of flash memory cells in a flash memory device using a...
SEMICONDUCTOR MEMORY DEVICE INCLUDING A DUMMY MEMORY CELL AND METHOD OF
PROGRAMMING THE SAME
A semiconductor memory and a method of programming the same are provided. A semiconductor memory device may include a memory cell array including a plurality...
NON-VOLATILE MEMORY AND METHOD WITH ADJUSTED TIMING FOR INDIVIDUAL
A non-volatile memory and method have programming circuitry that outputs a series of programming pulses of increasing voltage level to program in parallel a...
Programming Of Drain Side Word Line To Reduce Program Disturb And Charge
Techniques are provided for programming the memory cells of a drain-side edge word line of a set of word lines before programming memory cells of any other...
BLOCK REFRESH TO ADAPT TO NEW DIE TRIM SETTINGS
Systems, apparatuses, and methods may be provided that adapt to trim set advancement. Trim set advancement may be a change in trim sets over time. A cell of a...
PAGE BUFFER CIRCUIT FOR NAND FLASH MEMORY
A page buffer for a NAND flash memory array includes a pre-charge switch, a first switch, a read switch, a write switch, a latch, and a data switch. The...
EPROM CELL ARRAY, METHOD OF OPERATING THE SAME, AND MEMORY DEVICE
INCLUDING THE SAME
A memory cell array includes local blocks disposed in parallel with rows and arrayed along a direction parallel with columns, first selection lines being...
ARRAY ORGANIZATION AND ARCHITECTURE TO PERFORM RANGE-MATCH OPERATIONS WITH
CONTENT ADDRESSABLE MEMORY (CAM)...
An array organization and architecture for a content addressable memory (CAM) system. More specifically, a circuit is provided for that includes a first...
CONTENT ADDRESSABLE MEMORY ARRAY
A memory apparatus includes a content addressable memory, CAM, cell block including CAM cells and a random access memory (RAM), cell block including RAM cells....
RESISTIVE MEMORY DEVICE, RESISTIVE MEMORY SYSTEM, AND OPERATING METHOD
A method for operating a memory device includes sensing a temperature of the resistive memory device, setting a level of a set voltage or current for writing...
RESISTANCE CHANGE MEMORY AND FORMING METHOD OF THE RESISTANCE CHANGE
A resistance change memory has a resistance change device and a control circuit for controlling application of voltage to the resistance change device. The...
SB-TE-TI PHASE-CHANGE MEMORY MATERIAL AND TI-SB2TE3 PHASE-CHANGE MEMORY
An Sb--Te--Ti phase-change thin-film material applicable to a phase-change memory and preparation thereof. The Sb--Te--Ti phase-change memory material is...
RESISTIVE MEMORY DEVICE, RESISTIVE MEMORY SYSTEM, AND OPERATING METHOD
A method for operating a memory device includes sensing a change in temperature of the memory device, adjusting a level of a reference current for a read...
THRESHOLD VOLTAGE DISTRIBUTION DETERMINATION
Apparatuses and methods for threshold voltage (Vt) distribution determination are described. A number of apparatuses can include sense circuitry configured to...
MULTI-TASK CONCURRENT/PIPELINE NAND OPERATIONS ON ALL PLANES
This invention provides a 2-level BL-hierarchical NAND memory architecture and associated concurrent operations applicable to both 2D and 3D HiNAND2 memory...
TECHNIQUES FOR DATA RETENTION IN MEMORY CELLS DURING POWER INTERRUPTION
Volatile memory is described, comprising: (i) a first inverter comprising a first p-type field effect transistor (FET) connected to a first n-type FET; (ii) a...
Leakage-Current Abatement Circuitry for Memory Arrays
In one memory array embodiment, in order to compensate for bit-line leakage currents by OFF-state bit-cell access devices, a leakage-current reference circuit...
METHOD AND APPARATUS FOR A MEMORY MODULE TO ACCEPT A COMMAND IN MULTIPLE
Provided are a method and apparatus for a memory module to accept a command in multiple parts. A first half of a command is placed on a bus for a memory module...
MEMORY CIRCUIT AND REFRESH METHOD THEREOF
A memory circuit is provided. The memory circuit includes a memory array, a plurality of word lines and a memory controller. The memory array has a plurality...
Devices, Systems and Methods of Setting Machines
A self-refresh device, adopted in a memory array including a plurality of memory cells, includes a first word-line selecting module, which is enabled according...
Disclosed herein is a device that includes a memory cell array including plurality of word lines, a plurality of bit lines each intersecting the word lines and...
SELF-REFERENCED SENSE AMPLIFIER FOR SPIN TORQUE MRAM
Circuitry and a method provide a plurality of timed control and bias voltages to sense amplifiers and write drivers of a spin-torque magnetoresistive random...
METHOD OF WRITING TO A SPIN TORQUE MAGNETIC RANDOM ACCESS MEMORY
A spin-torque magnetoresistive memory includes array read circuits and array write circuits coupled to an array of magnetic bits. The array read circuits...
MEMORY DEVICE WITH SHARED READ/WRITE CIRCUITRY
In some examples, a memory device may be configured to read or write multiple bit cells as part of the same operation. In some cases, the tunnel junctions...
MEMORY DEVICE WITH DIFFERENTIAL BIT CELLS
In some examples, a memory device may be configured to utilize differential bit cells formed from two or more tunnel junctions. In some cases, the tunnel...
Magnetic Tunnel Junction Memory Device
A magnetic-assist, spin-torque transfer magnetic tunnel junction device and a method for performing a magnetic-assist, spin-torque-transfer write to the device...
VOLTAGE-CONTROLLED MAGNETIC ANISOTROPY (VCMA) SWITCH AND MAGNETO-ELECTRIC
Voltage controlled magnetic tunnel junctions and memory devices are described which provide efficient high speed switching of non-volatile magnetic devices at...
I/O PIN CAPACITANCE REDUCTION USING TSVS
Methods for reducing pin capacitance and improving off-chip driver performance by using TSVs to enable usage of off-chip drivers located within selected and...
COLUMN DECODER CIRCUITRY FOR A NON-VOLATILE MEMORY
A memory includes a column decoder performing at least two levels of decoding using a first level decoder that decodes between the column bit lines and first...
BI-SYNCHRONOUS ELECTRONIC DEVICE AND FIFO MEMORY CIRCUIT WITH JUMP
CANDIDATES AND RELATED METHODS
A bi-synchronous electronic device may include a FIFO memory circuit, and a first digital circuit coupled to the FIFO memory circuit and configured to operate...
BI-SYNCHRONOUS ELECTRONIC DEVICE WITH BURST INDICATOR AND RELATED METHODS
A bi-synchronous electronic device may include a FIFO memory circuit configured to store data, and a first digital circuit coupled to the FIFO memory circuit...
STROBE SIGNAL INTERVAL DETECTION CIRCUIT AND MEMORY SYSTEM INCLUDING THE
A strobe signal interval detection circuit may include an oscillator configured to generate a periodic signal at a preset cycle determined through a delay time...
TECHNIQUES TO BOOST WORD-LINE VOLTAGE USING PARASITIC CAPACITANCES
A memory device with word-line voltage boosting includes a set of first switches that are operable to couple a word-line of the memory device to a supply...
INTEGRATED CIRCUIT WITH INDEPENDENT PROGRAMMABILITY
An integrated circuit includes circuitry performing memory operations. The power from only one of a first power lead and a second power lead is sufficient for...
LOW POWER RADIATION HARDENED MEMORY CELL
The invention concerns a memory cell having: first and second cross-coupled gated inverters (102, 104), each including first and second inputs (IN1, IN2) and...
STORAGE METHOD, PLAYBACK METHOD, STORAGE APPARATUS, AND PLAYBACK APPARATUS
A storage method according to one aspect includes: a reception step of receiving a coded stream including a plurality of files that are of a data unit in a...
POINT OF VIEW VIDEO PROCESSING AND CURATION PLATFORM
Embodiments of the present disclosure may provide methods and systems enabled to receive a plurality of streams comprising at least one video stream and at...
METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR EDITING MOVIES IN
DISTRIBUTED SCALABLE MEDIA ENVIRONMENT
A movie editor converts a received movie into a proxy format, and creates a texture strip representing the frames of the movie. An editor can use the texture...
AUTOMATIC GENERATION OF COMPILATION VIDEOS
Embodiments described herein include systems and methods for automatically creating compilation videos from an original video based on metadata associated with...
Systems and Methods For Motion-Vector-Aided Video Interpolation Using
Real-Time Smooth Video Playback Speed...
Systems and methods for encoding and playing back video at adjustable playback speeds by interpolating frames to achieve smooth playback in accordance with...
MULTI-SPEED PROGRAMMABLE BATCH SCRUBBER SYSTEM
Systems and methods for a multi-speed programmable batch scrubber are illustrated. The disclosed system includes a brush configured to scrub a disk at a...
Perpendicular Recording Media with Enhanced Anisotropy Through Energy
Apparatus for recording data and method for making the same. In accordance with some embodiments, a magnetic layer is supported by a substrate and comprises a...
WRITER POLE FORMATION
Implementations disclosed herein provide a method of reducing the topography at the alignment and overlay marks area during the writer pole photolithography...
MAGNETIC RECORDING MEDIUM
A magnetic recording medium includes a flexible substrate, an amorphous seed layer, an under layer containing Ru, and a recording layer having a granular...
LAYERED SEGREGANT HEAT ASSISTED MAGNETIC RECORDING (HAMR) MEDIA
According to one embodiment, a magnetic recording medium includes a substrate, and a magnetic recording layer structure positioned above the substrate, the...
MAGNETIC STACK INCLUDING MgO-Ti(ON) INTERLAYER
A stack includes a substrate and a magnetic recording layer. Disposed between the substrate and magnetic recording layer is an MgO--Ti(ON) layer.