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Patent # Description
2016/0099065 LATCH INITIALIZATION FOR A DATA STORAGE DEVICE
A data storage device may include a memory die. The memory die includes a memory and a latch. A method may include receiving a command corresponding to a write...
2016/0099064 NON-VOLATILE SEMICONDUCTOR MEMORY WITH HIGH RELIABILITY AND DATA ERASING METHOD THEREOF
A non-volatile semiconductor memory apparatus and a data erasing method thereof are provided to suppress deterioration in reliability due to data rewriting. An...
2016/0099063 SEMICONDUCTOR DEVICE
A semiconductor device includes memory strings each including a drain select transistor, memory cells and a source select transistor, which are connected...
2016/0099062 DATA WRITING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT
A data writing method, a memory storage device, and a memory control circuit unit are provided. The method includes: writing data into at least one first...
2016/0099061 FAST SECURE ERASE IN A FLASH SYSTEM
A flash memory controller is configured to provide a first erase mode for erasing one or more groups of flash memory cells in a flash memory device using a...
2016/0099060 SEMICONDUCTOR MEMORY DEVICE INCLUDING A DUMMY MEMORY CELL AND METHOD OF PROGRAMMING THE SAME
A semiconductor memory and a method of programming the same are provided. A semiconductor memory device may include a memory cell array including a plurality...
2016/0099059 NON-VOLATILE MEMORY AND METHOD WITH ADJUSTED TIMING FOR INDIVIDUAL PROGRAMMING PULSES
A non-volatile memory and method have programming circuitry that outputs a series of programming pulses of increasing voltage level to program in parallel a...
2016/0099058 Programming Of Drain Side Word Line To Reduce Program Disturb And Charge Loss
Techniques are provided for programming the memory cells of a drain-side edge word line of a set of word lines before programming memory cells of any other...
2016/0099057 BLOCK REFRESH TO ADAPT TO NEW DIE TRIM SETTINGS
Systems, apparatuses, and methods may be provided that adapt to trim set advancement. Trim set advancement may be a change in trim sets over time. A cell of a...
2016/0099056 PAGE BUFFER CIRCUIT FOR NAND FLASH MEMORY
A page buffer for a NAND flash memory array includes a pre-charge switch, a first switch, a read switch, a write switch, a latch, and a data switch. The...
2016/0099055 EPROM CELL ARRAY, METHOD OF OPERATING THE SAME, AND MEMORY DEVICE INCLUDING THE SAME
A memory cell array includes local blocks disposed in parallel with rows and arrayed along a direction parallel with columns, first selection lines being...
2016/0099054 ARRAY ORGANIZATION AND ARCHITECTURE TO PERFORM RANGE-MATCH OPERATIONS WITH CONTENT ADDRESSABLE MEMORY (CAM)...
An array organization and architecture for a content addressable memory (CAM) system. More specifically, a circuit is provided for that includes a first...
2016/0099053 CONTENT ADDRESSABLE MEMORY ARRAY
A memory apparatus includes a content addressable memory, CAM, cell block including CAM cells and a random access memory (RAM), cell block including RAM cells....
2016/0099052 RESISTIVE MEMORY DEVICE, RESISTIVE MEMORY SYSTEM, AND OPERATING METHOD THEREOF
A method for operating a memory device includes sensing a temperature of the resistive memory device, setting a level of a set voltage or current for writing...
2016/0099051 RESISTANCE CHANGE MEMORY AND FORMING METHOD OF THE RESISTANCE CHANGE DEVICE
A resistance change memory has a resistance change device and a control circuit for controlling application of voltage to the resistance change device. The...
2016/0099050 SB-TE-TI PHASE-CHANGE MEMORY MATERIAL AND TI-SB2TE3 PHASE-CHANGE MEMORY MATERIAL
An Sb--Te--Ti phase-change thin-film material applicable to a phase-change memory and preparation thereof. The Sb--Te--Ti phase-change memory material is...
2016/0099049 RESISTIVE MEMORY DEVICE, RESISTIVE MEMORY SYSTEM, AND OPERATING METHOD THEREOF
A method for operating a memory device includes sensing a change in temperature of the memory device, adjusting a level of a reference current for a read...
2016/0099048 THRESHOLD VOLTAGE DISTRIBUTION DETERMINATION
Apparatuses and methods for threshold voltage (Vt) distribution determination are described. A number of apparatuses can include sense circuitry configured to...
2016/0099047 MULTI-TASK CONCURRENT/PIPELINE NAND OPERATIONS ON ALL PLANES
This invention provides a 2-level BL-hierarchical NAND memory architecture and associated concurrent operations applicable to both 2D and 3D HiNAND2 memory...
2016/0099046 TECHNIQUES FOR DATA RETENTION IN MEMORY CELLS DURING POWER INTERRUPTION
Volatile memory is described, comprising: (i) a first inverter comprising a first p-type field effect transistor (FET) connected to a first n-type FET; (ii) a...
2016/0099045 Leakage-Current Abatement Circuitry for Memory Arrays
In one memory array embodiment, in order to compensate for bit-line leakage currents by OFF-state bit-cell access devices, a leakage-current reference circuit...
2016/0099044 METHOD AND APPARATUS FOR A MEMORY MODULE TO ACCEPT A COMMAND IN MULTIPLE PARTS
Provided are a method and apparatus for a memory module to accept a command in multiple parts. A first half of a command is placed on a bus for a memory module...
2016/0099043 MEMORY CIRCUIT AND REFRESH METHOD THEREOF
A memory circuit is provided. The memory circuit includes a memory array, a plurality of word lines and a memory controller. The memory array has a plurality...
2016/0099042 Devices, Systems and Methods of Setting Machines
A self-refresh device, adopted in a memory array including a plurality of memory cells, includes a first word-line selecting module, which is enabled according...
2016/0099041 Semiconductor Device
Disclosed herein is a device that includes a memory cell array including plurality of word lines, a plurality of bit lines each intersecting the word lines and...
2016/0099040 SELF-REFERENCED SENSE AMPLIFIER FOR SPIN TORQUE MRAM
Circuitry and a method provide a plurality of timed control and bias voltages to sense amplifiers and write drivers of a spin-torque magnetoresistive random...
2016/0099039 METHOD OF WRITING TO A SPIN TORQUE MAGNETIC RANDOM ACCESS MEMORY
A spin-torque magnetoresistive memory includes array read circuits and array write circuits coupled to an array of magnetic bits. The array read circuits...
2016/0099038 MEMORY DEVICE WITH SHARED READ/WRITE CIRCUITRY
In some examples, a memory device may be configured to read or write multiple bit cells as part of the same operation. In some cases, the tunnel junctions...
2016/0099037 MEMORY DEVICE WITH DIFFERENTIAL BIT CELLS
In some examples, a memory device may be configured to utilize differential bit cells formed from two or more tunnel junctions. In some cases, the tunnel...
2016/0099036 Magnetic Tunnel Junction Memory Device
A magnetic-assist, spin-torque transfer magnetic tunnel junction device and a method for performing a magnetic-assist, spin-torque-transfer write to the device...
2016/0099035 VOLTAGE-CONTROLLED MAGNETIC ANISOTROPY (VCMA) SWITCH AND MAGNETO-ELECTRIC MEMORY (MERAM)
Voltage controlled magnetic tunnel junctions and memory devices are described which provide efficient high speed switching of non-volatile magnetic devices at...
2016/0099034 I/O PIN CAPACITANCE REDUCTION USING TSVS
Methods for reducing pin capacitance and improving off-chip driver performance by using TSVs to enable usage of off-chip drivers located within selected and...
2016/0099033 COLUMN DECODER CIRCUITRY FOR A NON-VOLATILE MEMORY
A memory includes a column decoder performing at least two levels of decoding using a first level decoder that decodes between the column bit lines and first...
2016/0099032 BI-SYNCHRONOUS ELECTRONIC DEVICE AND FIFO MEMORY CIRCUIT WITH JUMP CANDIDATES AND RELATED METHODS
A bi-synchronous electronic device may include a FIFO memory circuit, and a first digital circuit coupled to the FIFO memory circuit and configured to operate...
2016/0099031 BI-SYNCHRONOUS ELECTRONIC DEVICE WITH BURST INDICATOR AND RELATED METHODS
A bi-synchronous electronic device may include a FIFO memory circuit configured to store data, and a first digital circuit coupled to the FIFO memory circuit...
2016/0099030 STROBE SIGNAL INTERVAL DETECTION CIRCUIT AND MEMORY SYSTEM INCLUDING THE SAME
A strobe signal interval detection circuit may include an oscillator configured to generate a periodic signal at a preset cycle determined through a delay time...
2016/0099029 TECHNIQUES TO BOOST WORD-LINE VOLTAGE USING PARASITIC CAPACITANCES
A memory device with word-line voltage boosting includes a set of first switches that are operable to couple a word-line of the memory device to a supply...
2016/0099028 INTEGRATED CIRCUIT WITH INDEPENDENT PROGRAMMABILITY
An integrated circuit includes circuitry performing memory operations. The power from only one of a first power lead and a second power lead is sufficient for...
2016/0099027 LOW POWER RADIATION HARDENED MEMORY CELL
The invention concerns a memory cell having: first and second cross-coupled gated inverters (102, 104), each including first and second inputs (IN1, IN2) and...
2016/0099026 STORAGE METHOD, PLAYBACK METHOD, STORAGE APPARATUS, AND PLAYBACK APPARATUS
A storage method according to one aspect includes: a reception step of receiving a coded stream including a plurality of files that are of a data unit in a...
2016/0099025 POINT OF VIEW VIDEO PROCESSING AND CURATION PLATFORM
Embodiments of the present disclosure may provide methods and systems enabled to receive a plurality of streams comprising at least one video stream and at...
2016/0099024 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR EDITING MOVIES IN DISTRIBUTED SCALABLE MEDIA ENVIRONMENT
A movie editor converts a received movie into a proxy format, and creates a texture strip representing the frames of the movie. An editor can use the texture...
2016/0099023 AUTOMATIC GENERATION OF COMPILATION VIDEOS
Embodiments described herein include systems and methods for automatically creating compilation videos from an original video based on metadata associated with...
2016/0099022 Systems and Methods For Motion-Vector-Aided Video Interpolation Using Real-Time Smooth Video Playback Speed...
Systems and methods for encoding and playing back video at adjustable playback speeds by interpolating frames to achieve smooth playback in accordance with...
2016/0099021 MULTI-SPEED PROGRAMMABLE BATCH SCRUBBER SYSTEM
Systems and methods for a multi-speed programmable batch scrubber are illustrated. The disclosed system includes a brush configured to scrub a disk at a...
2016/0099020 Perpendicular Recording Media with Enhanced Anisotropy Through Energy Assisted Segregation
Apparatus for recording data and method for making the same. In accordance with some embodiments, a magnetic layer is supported by a substrate and comprises a...
2016/0099019 WRITER POLE FORMATION
Implementations disclosed herein provide a method of reducing the topography at the alignment and overlay marks area during the writer pole photolithography...
2016/0099018 MAGNETIC RECORDING MEDIUM
A magnetic recording medium includes a flexible substrate, an amorphous seed layer, an under layer containing Ru, and a recording layer having a granular...
2016/0099017 LAYERED SEGREGANT HEAT ASSISTED MAGNETIC RECORDING (HAMR) MEDIA
According to one embodiment, a magnetic recording medium includes a substrate, and a magnetic recording layer structure positioned above the substrate, the...
2016/0099016 MAGNETIC STACK INCLUDING MgO-Ti(ON) INTERLAYER
A stack includes a substrate and a magnetic recording layer. Disposed between the substrate and magnetic recording layer is an MgO--Ti(ON) layer.
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