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Patent # Description
2016/0104817 LED PACKAGE
The present disclosure provides a light emitting diode die which includes a substrate; an N type semiconductor layer, an active layer, and a P type ...
2016/0104816 LIGHT EMITTING DEVICE AND METHOD FOR PREPARING THE SAME
Provided are a light-emitting element and a method for preparing same. The method includes a method for growing a p-type semiconductor layer having a...
2016/0104815 THIN-FILM FLIP-CHIP LIGHT EMITTING DIODE HAVING ROUGHENING SURFACE AND METHOD FOR MANUFACTURING THE SAME
A thin-film flip-chip light emitting diode (LED) having a roughened surface and a method for manufacturing the same are provided. First, a substrate having a...
2016/0104814 VERTICAL-TYPE SEMICONDUCTOR LIGHT-EMMITTING DEVICE AND METHOD OF FABRICATING THE VERTICAL-TYPE LIGHT-EMITTING...
A semiconductor light-emitting device includes an active layer and a first semiconductor layer sequentially stacked on a second semiconductor layer and...
2016/0104813 METHOD FOR PROCESSING DEVICES INCLUDING QUANTUM DOTS AND DEVICES
A method of processing quantum dots is disclosed. The method comprises applying energy to excite the quantum dots to emit light and placing the quantum dots...
2016/0104812 INTEGRATED PHOTODIODE FOR SEMICONDUCTOR SUBSTRATES
A substrate section that is at least partially fabricated to include contact elements and materials. The substrate section includes doped regions that have a...
2016/0104811 SOLAR CELL AND METHOD OF FABRICATING THE SAME
A solar cell is provided. The solar cell includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second...
2016/0104810 SOLAR CELL MODULE AND METHOD FOR PRODUCING SAME
A solar cell module having low resistance loss between a collector electrode and a connection wiring line, and a method for producing the solar cell module. A...
2016/0104809 A BACKSHEET FOR PHOTOVOLTAIC MODULES
A backsheet for a photovoltaic module includes a support and a weather resistant layer, the weather resistant layer including a crosslinking agent, a first...
2016/0104808 METHOD FOR PRODUCING THE P-N JUNCTION OF A THIN-FILM PHOTOVOLTAIC CELL AND CORRESPONDING METHOD FOR PRODUCING A...
A method for producing a P-N junction in a thin film photovoltaic cell comprising a deposition step in which are carried out successively: a layer of...
2016/0104807 SOLAR CELL
A solar cell includes a support substrate; a back electrode layer on the a support substrate; a light absorbing layer on the back electrode layer; a buffer...
2016/0104806 HEATED IMAGE SENSOR WINDOW
An image sensor assembly having a sensor window positioned in front of an image sensor, having structure and/or characteristics to prevent the formation of...
2016/0104805 OPTICAL SEMICONDUCTOR DEVICE INCLUDING BLACKENED TARNISHABLE BOND WIRES AND RELATED METHODS
A method for making an optical semiconductor device may include forming an integrated circuit (IC) including an optical sensing area and a bond pads outside...
2016/0104804 SELF-ALIGNED THIN FILM TRANSISTOR AND FABRICATION METHOD THEREOF
Disclosed are a self-aligned thin film transistor capable of simultaneously improving an operation speed and stability and minimizing a size thereof by forming...
2016/0104803 DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME
A display substrate includes a base substrate, a gate pattern, an active pattern and a data metal pattern. The gate pattern includes a gate electrode on the...
2016/0104802 NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT, NONVOLATILE SEMICONDUCTOR MEMORY, AND METHOD FOR OPERATING...
According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a...
2016/0104801 MEMORY DEVICES, METHODS OF MANUFACTURING THE SAME, AND METHODS OF ACCESSING THE SAME
Memory devices, methods of manufacturing the same, and methods of accessing the same are provided. In one embodiment, the memory device may include a...
2016/0104800 Body-Tied, Strained-Channel Multi-Gate Device and Methods of Manufacturing Same
A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor...
2016/0104799 DUAL-STRAINED NANOWIRE AND FINFET DEVICES WITH DIELECTRIC ISOLATION
A dual-strained Si and SiGe FinFET device with dielectric isolation and a dual-strained nanowire device and methods of forming them are provided. Embodiments...
2016/0104798 VERTICAL-CHANNEL SEMICONDUCTOR DEVICE
A vertical-channel semiconductor device having a buried bit line is disclosed. The vertical-channel semiconductor device enables an active pillar including a...
2016/0104797 Semiconductor Device and Method of Manufacturing a Semiconductor Device
A semiconductor device comprises a gate electrode in a trench in a semiconductor body. The gate electrode comprises a plurality of gate segments disposed along...
2016/0104796 METHOD OF FORMING A SEMICONDUCTOR DEVICE
In one embodiment, a method of forming a semiconductor device may include forming a buried region within a semiconductor region, including forming an opening...
2016/0104795 SEMICONDUCTOR DEVICE
A semiconductor device includes a second conductivity type back gate electrode formed within a body area, and electrically connected with the body area, and...
2016/0104794 SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
A silicon carbide semiconductor device includes: a vertical MOSFET having: a semiconductor substrate including a high-concentration impurity layer and a drift...
2016/0104793 Structure and Method for FinFET Device
The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a fin structure disposed over a...
2016/0104792 HIGH VOLTAGE MOSFET DEVICES AND METHODS OF MAKING THE DEVICES
A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+...
2016/0104791 METHOD FOR FORMING AN IMPLANTED AREA FOR A HETEROJUNCTION TRANSISTOR THAT IS NORMALLY BLOCKED
The invention relates to a method for manufacturing a heterojunction transistor (1), said method comprising the steps of: forming an implanted area (8) by...
2016/0104790 SILICENE MATERIAL LAYER AND ELECTRONIC DEVICE HAVING THE SAME
Provided are silicene material layers and electronic devices having a silicene material layer. The silicene material layer contains silicon atoms in a...
2016/0104789 SONOS Type Stacks for Nonvolatile ChangeTrap Memory Devices and Methods to Form the Same
A method includes forming a first oxide layer. The method further includes etching a portion of the first oxide layer using a first decoupled plasma...
2016/0104788 Methods of Fabricating Semiconductor Devices
Semiconductor devices and methods of fabricating semiconductor devices are provided. The methods may include forming an interlayer insulation layer on a...
2016/0104787 METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING CONDUCTIVE CONTACTS ON SOURCE/DRAINS
Methods of forming a semiconductor device are provided. The methods may include forming a plurality of fin-shaped channels on a substrate, forming a gate...
2016/0104786 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer...
2016/0104785 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first gate layer and a first...
2016/0104784 Ohmic Contact to Semiconductor
A solution for forming an ohmic contact to a semiconductor layer is provided. A masking material is applied to a set of contact regions on the surface of the...
2016/0104783 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device and a method for manufacturing the same are disclosed, which include a gate electrode material in a recess or a buried gate cell...
2016/0104782 TRANSISTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME
A method of manufacturing a transistor structure includes a step of implanting a light dosage into a substrate at a bit line junction and two cell side...
2016/0104781 INTEGRATED FLOATING DIODE STRUCTURE AND METHOD THEREFOR
In one embodiment, a floating diode structure includes a p-type semiconductor substrate. An n-type doped region is disposed between the semiconductor substrate...
2016/0104780 Semiconductor Devices and Methods of Manufacturing Thereof
In one embodiment, a method of forming a semiconductor device includes forming a first porous semiconductor layer over a top surface of a substrate. A first...
2016/0104779 SILICON CARBIDE DEVICE AND A METHOD FOR FORMING A SILICON CARBIDE DEVICE
A silicon carbide device includes a silicon carbide substrate, an inorganic passivation layer structure and a molding material layer. The inorganic passivation...
2016/0104778 GRAPHENE BASE TRANSISTOR AND METHOD FOR MAKING THE SAME
A graphene base transistor comprises on a semiconductor substrate surface an emitter pillar and an emitter-contact pillar, which extend from a pillar...
2016/0104777 Zero-Dimensional Electron Devices and Methods of Fabricating the Same
A semiconductor device comprises a substrate and quantum dots, wherein a peak emission of the quantum dots has a FWHM of less than 20 meV when the ...
2016/0104776 High Mobility Devices with Anti-Punch Through Layer and Methods of Forming Same
An embodiment semiconductor device includes a fin extending upwards from a semiconductor substrate. The fin includes an anti-punch through (APT) layer having...
2016/0104775 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device includes a buffer layer on a semiconductor substrate including first and second regions, a first channel layer on the buffer layer of...
2016/0104774 NON-PLANAR VERTICAL DUAL SOURCE DRIFT METAL-OXIDE SEMICONDUCTOR (VDSMOS)
A non-planar lateral drift MOS device eliminates the need for a field plate extension, which reduces gate width. In one example, two sources and two...
2016/0104773 Semiconductor Structure Having Integrated Snubber Resistance and Related Method
A semiconductor structure is disclosed. The semiconductor structure includes a source trench in a drift region, the source trench having a source trench...
2016/0104772 METHOD OF MAKING A SEMICONDUCTOR DEVICE USING A DUMMY GATE
A method of making a semiconductor device includes forming a fin mask layer on a semiconductor layer, forming a dummy gate over the fin mask layer, and forming...
2016/0104771 COMMON CONTACT OF N++ AND P++ TRANSISTOR DRAIN REGIONS IN CMOS
Implementations of the present disclosure relate to semiconductor devices such as transistors used for amplifying or switching electronic signals. In one...
2016/0104770 PROFILE CONTROL OVER A COLLECTOR OF A BIPOLAR JUNCTION TRANSISTOR
Device structures for a bipolar junction transistor. A layer is formed on a top surface of a substrate. A trench is formed in the layer and has a plurality of...
2016/0104769 LAYERED STRUCTURE OF A P-TFET
A p-type Tunnel Field-Effect Transistor comprises a drain p-type semiconductor region, a source n-type semiconductor region, and at least one gate stack. The...
2016/0104768 Method of Forming a Super Junction Semiconductor Device Having Stripe-Shaped Regions of the Opposite...
A super junction semiconductor device is formed by forming at least a portion of a drift layer on a doped layer of a first conductivity type, implanting first...
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