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Patent # Description
2016/0104717 APPARATUSES AND METHODS FOR FORMING MULTIPLE DECKS OF MEMORY CELLS
Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck...
2016/0104716 METHODS OF FORMING INTEGRATED CIRCUIT DEVICES
Methods of forming integrated circuit devices containing memory cells over a first region of a semiconductor substrate and gate structures over a second region...
2016/0104715 MULTILEVEL MEMORY STACK STRUCTURE AND METHODS OF MANUFACTURING THE SAME
A first stack of alternating layers including first electrically conductive layers and first electrically insulating layers is formed with first stepped...
2016/0104714 SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF PRODUCING THE SAME
Provided is a semiconductor integrated circuit that uses a novel vertical MOS transistor that is free of interference between cells, that enables the...
2016/0104713 WING-TYPE PROJECTION BETWEEN NEIGHBORING ACCESS TRANSISTORS IN MEMORY DEVICES
A flash memory device is disposed on a semiconductor substrate. The flash memory device includes flash memory cells arranged in rows and columns. Respective...
2016/0104712 ONE TIME PROGRAMMABLE NON-VOLATILE MEMORY
A one time programmable (OTP) non-volatile memory including a substrate, a switch device and a fuse structure is provided. The switch device is disposed on the...
2016/0104711 NON-VOLATILE MEMORY
A non-volatile memory including a substrate, a floating gate transistor, a select transistor and a stress-releasing transistor. The floating gate transistor,...
2016/0104710 SELF ALIGNED ACTIVE TRENCH CONTACT
An integrated circuit and method includes self-aligned contacts. A gapfill dielectric layer fills spaces between sidewalls of adjacent MOS gates. The gapfill...
2016/0104709 PASSING ACCESS LINE STRUCTURE IN A MEMORY DEVICE
A method for memory device fabrication includes forming a plurality of continuous fins on a substrate. An insulator material is formed around the fins. The...
2016/0104708 SEMICONDUCTOR DEVICES HAVING ACTIVE REGIONS AT DIFFERENT LEVELS
A semiconductor device has active regions with different conductivity types. A substrate has a PMOS region and an NMOS region. A first active region is in the...
2016/0104707 METHOD AND STRUCTURE FOR TRANSISTORS USING GATE STACK DOPANTS WITH MINIMAL NITROGEN PENETRATION
Embodiments of the present invention provide CMOS structures and methods of gate formation that combine a keep-cap scheme in which a protective layer is...
2016/0104706 FIN-LIKE FIELD EFFECT TRANSISTOR (FINFET) DEVICE AND METHOD OF MANUFACTURING SAME
A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes providing a semiconductor substrate; forming a first fin...
2016/0104705 SEMICONDUCTOR DEVICE INCLUDING FINFETS HAVING DIFFERENT GATE STRUCTURES AND METHOD OF MANUFACTURING THE...
A semiconductor device includes a substrate having a logic device region including logic devices thereon, and an input/output (I/O) device region including I/O...
2016/0104704 SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a first fin structure and a second fin structure...
2016/0104703 INTEGRATED ENHANCEMENT MODE AND DEPLETION MODE DEVICE STRUCTURE AND METHOD OF MAKING THE SAME
A circuit is provided that includes a castellated channel device that comprises a heterostructure overlying a substrate structure, a castellated channel device...
2016/0104702 SUPER-JUNCTION TRENCH MOSFET INTEGRATED WITH EMBEDDED TRENCH SCHOTTKY RECTIFIER
A super-junction trench MOSFET integrated with embedded trench Schottky rectifier is disclosed for soft reverse recovery operation. The embedded trench...
2016/0104701 SEMICONDUCTOR DEVICE INCLUDING ESD PROTECTION CIRCUIT
A semiconductor device including an electrostatic discharge (ESD) protection circuit includes an input port, a logic circuit receiving an input signal applied...
2016/0104700 ELECTROSTATIC DISCHARGE PROTECTION DEVICE
The present disclosure relates to an electrostatic discharge (ESD) protection device. The electrostatic discharge protection device, may comprise: a...
2016/0104699 SEMICONDUCTOR APPARATUS
There is provided a semiconductor apparatus comprising: a first switching element formed of a wide band gap semiconductor; and a second switching element...
2016/0104698 METHOD FOR MAKING AN OPTICAL PROXIMITY SENSOR
A method for making an optical proximity sensor includes forming a package top plate having an optical transmit opening and an optical receive opening...
2016/0104697 Compact High-Voltage Semiconductor Package
There are disclosed herein various implementations of a compact high-voltage semiconductor package. In one exemplary implementation, such a semiconductor...
2016/0104696 TECHNIQUES FOR TILING ARRAYS OF PIXEL ELEMENTS AND FABRICATING HYBRIDIZED TILES
A first substrate having an array of emitters or detectors may be joined by bump bonding with a second substrate having read-in (RIIC) or read-out (ROIC)...
2016/0104695 TRANSFER-BONDING METHOD FOR THE LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE ARRAY
A light emitting device array including a circuit substrate and a plurality of device layers is provided. The circuit substrate includes a plurality of bonding...
2016/0104694 Packaged Semiconductor Devices and Packaging Methods Thereof
Packaged semiconductor devices and methods of packaging thereof are disclosed. In some embodiments, a packaged semiconductor device includes a first device and...
2016/0104693 INTERCONNECT STRUCTURES WITH INTERMETALLIC PALLADIUM JOINTS AND ASSOCIATED SYSTEMS AND METHODS
Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, a method of forming an interconnect structure includes...
2016/0104692 DISPLAY DEVICE
A display device includes a panel substrate including a pad region, and a COF (Chip On Film) including a wire region, the wire region including a plurality of...
2016/0104691 SUPER CMOS DEVICES ON A MICROELECTRONICS SYSTEM
A low cost IC solution is disclosed in accordance with an embodiment to provide Super CMOS microelectronics macros. Hereinafter, the Super CMOS or Schottky...
2016/0104690 BONDING PROCESS FOR A CHIP BONDING TO A THIN FILM SUBSTRATE
A bonding process for a chip bonded to a thin film substrate is disclosed. The thin film substrate has a thickness of about less than 500 um. Curvature occurs...
2016/0104689 SEMICONDUCTOR DIE MOUNT BY CONFORMAL DIE COATING
A conformal coating on a semiconductor die provides adhesion between the die and a support. No additional adhesive is necessary to affix the die on the...
2016/0104688 Robust and Reliable Power Semiconductor Package
In one implementation, a semiconductor package includes a patterned conductive carrier including a support segment having a partially etched recess. The...
2016/0104687 BONDING WIRE FOR SEMICONDUCTOR DEVICE USE AND METHOD OF PRODUCTION OF SAME
Bonding wire for semiconductor device use where both leaning failures and spring failures are suppressed by (1) in a cross-section containing the wire center...
2016/0104686 DRIVING CHIP AND DISPLAY DEVICE
A driving chip and a display device, relating to the technical field of driving chip for displays, are disclosed. A surface of the driving chip has a first...
2016/0104685 Improving the Strength of Micro-Bump Joints
A device includes a work piece including a metal bump; and a dielectric layer having a portion directly over the metal bump. The metal bump and a surface of...
2016/0104684 SEMICONDUCTOR MEMORY DEVICE HAVING PADS
A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor...
2016/0104683 INTEGRATED CIRCUIT DEVICE AND ELECTROSTATIC DISCHARGE PROTECTION DEVICE THEREOF
An integrated circuit (IC) device includes an IC and an electrostatic discharge (ESD) protection device. The IC has a substrate, a core and a power mesh. The...
2016/0104682 Crack Stop Barrier and Method of Manufacturing Thereof
A wafer is disclosed. The wafer comprises a plurality of chips and a plurality of kerfs. A kerf of the plurality of kerfs separates one chip from another chip....
2016/0104681 Semiconductor Device and Method of Forming Prefabricated Heat Spreader Frame with Embedded Semiconductor Die
A semiconductor device is made by mounting a prefabricated heat spreader frame over a temporary substrate. The heat spreader frame includes vertical bodies...
2016/0104680 METHOD OF FORMING METAL INTERCONNECTIONS OF SEMICONDUCTOR DEVICE
A method of forming a metal interconnection of semiconductor device is provided. The method includes forming a low-k dielectric layer including an opening;...
2016/0104679 METHODS OF FORMING SUBSTRATE MICROVIAS WITH ANCHOR STRUCTURES
Methods of forming anchor structures in package substrate microvias are described. Those methods and structures may include forming a titanium layer in an...
2016/0104678 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
In a semiconductor device, a first gate structure having a first end portion is formed on a substrate. A second gate structure is formed on the substrate, and...
2016/0104677 SELF ALIGNED VIA FUSE
A method including forming a first via opening in a substrate, the first via opening is self-aligned to a first trench in the substrate, forming a second via...
2016/0104676 METALLISATION FOR SEMICONDUCTOR DEVICE
The present disclosure relates to a semiconductor device comprising a metallisation stack. The metallisation stack may include a first metallisation layer and...
2016/0104675 INTERCONNECTS THROUGH DIELECRIC VIAS
A dielectric layer includes a reflow via. The reflow via is formed by reflow of the dielectric layer. An interconnect is in contact through the reflow via.
2016/0104674 INTEGRATED CIRCUIT WITH ELONGATED COUPLING
An integrated circuit comprises a first layer on a first level. The first layer comprises a set of first lines. The first lines each have a length and a width....
2016/0104673 FIN-SHAPED FIELD-EFFECT TRANSISTOR WITH A GERMANIUM EPITAXIAL CAP AND A METHOD FOR FABRICATING THE SAME
A FinFET includes a fin-shaped structure, a gate structure, an epitaxial layer, an interlayer dielectric layer, an opening, a germanium cap and a contact plug....
2016/0104672 LOW CAPACITANCE BALLISTIC CONDUCTOR SIGNAL LINES
A method of electrically connecting first and second conductive features includes forming a first metallization layer including the first conductive feature. A...
2016/0104671 SEMICONDUCTOR DEVICES INCLUDING BIT LINE CONTACT PLUG AND PERIPHERAL TRANSISTOR
A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active...
2016/0104670 INTERLAYER BALLISTIC CONDUCTOR SIGNAL LINES
A method includes forming a ballistic conductor line above a first metallization layer. A dielectric layer is formed above the ballistic conductor line. A...
2016/0104669 SEMICONDUCTOR STRUCTURE WITH IMPROVED METALLIZATION ADHESION AND METHOD FOR MANUFACTURING THE SAME
A semiconductor structure is disclosed. The semiconductor structure may include a substrate, a first layer formed on a first side of the substrate and second...
2016/0104668 POP JOINT THROUGH INTERPOSER
A package includes a package component and an interposer over and bonded to the package component. The package component includes a solder region. The...
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