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Patent # Description
2016/0111535 SEMICONDUCTOR DEVICE WITH ONE-SIDE-CONTACT AND METHOD FOR FABRICATING THE SAME
A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a...
2016/0111534 DUAL GATE FD-SOI TRANSISTOR
Circuit module designs that incorporate dual gate field effect transistors are implemented with fully depleted silicon-on-insulator (FD-SOI) technology....
2016/0111533 SILICON CARBIDE SEMICONDUCTOR DEVICE
A silicon carbide (SiC) semiconductor device having a metal oxide semiconductor field effect transistor (MOSFET) and integrated with an anti-parallelly...
2016/0111532 SOURCE/DRAIN CONTACTS FOR NON-PLANAR TRANSISTORS
The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description...
2016/0111531 Semiconductor Devices Including Channel Regions with Varying Widths
A semiconductor device includes a semiconductor substrate, a fin-type structure on the semiconductor substrate, and a gate on a portion of a top surface and...
2016/0111530 Structure of a Trench MOS Rectifier and Method of Forming the Same
A structure of trench MOS rectifier and a method of forming the same are disclosed including a plurality of trenches formed in the n- drift epitaxial layer, a...
2016/0111529 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor substrate. Dummy trenches and a grid-structured gate trench located between the dummy trenches are provided in...
2016/0111528 Semiconductor Device with Auxiliary Structure Including Deep Level Dopants
A semiconductor device includes transistor cells formed along a first surface at a front side of a semiconductor body in a transistor cell area. A drift zone...
2016/0111527 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH FIN-SHAPED STRUCTURE
A method for fabricating semiconductor device with fin-shaped structure is disclosed. The method includes the steps of: forming a fin-shaped structure on a...
2016/0111526 Forming Conductive STI Liners for FinFETs
An integrated circuit device, and a method of forming, including a semiconductor substrate, isolation regions extending into the semiconductor substrate, a...
2016/0111525 FIN FORMATION IN FIN FIELD EFFECT TRANSISTORS
A method of forming a semiconductor device that includes forming a silicon including fin structure and forming a germanium including layer on the silicon...
2016/0111524 SEMICONDUCTOR DEVICES INCLUDING A GATE CORE AND A FIN ACTIVE CORE AND METHODS OF FABRICATING THE SAME
Semiconductor devices and methods of fabricating the same are provided. The methods may include forming an isolation region defining a fin active region,...
2016/0111523 METHOD OF FORMING A VERTICAL DEVICE
According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming...
2016/0111522 ENHANCED GATE REPLACEMENT PROCESS FOR HIGH-K METAL GATE TECHNOLOGY
The present disclosure provides a method of fabricating a semiconductor device. A high-k dielectric layer is formed over a substrate. A first capping layer is...
2016/0111521 THRESHOLD ADJUSTMENT FOR QUANTUM DOT ARRAY DEVICES WITH METAL SOURCE AND DRAIN
Incorporation of metallic quantum dots (e.g., silver bromide (AgBr) films) into the source and drain regions of a MOSFET can assist in controlling the...
2016/0111520 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING A BARRIER STRUCTURE
A method of manufacturing a semiconductor device includes forming a barrier structure over a substrate. The method further includes forming a channel layer...
2016/0111519 INSULATED GATE BIPOLAR TRANSISTOR WITH A LATERAL GATE STRUCTURE AND GALLIUM NITRIDE SUBSTRATE AND MANUFACTURING...
The present invention discloses an insulated gate bipolar transistor (IGBT) and a manufacturing method thereof. The IGBT includes: a gallium nitride (GaN)...
2016/0111518 Method and Structure for FinFET
A semiconductor device and method of forming the same are disclosed. The method includes receiving a substrate having an active fin, an oxide layer over the...
2016/0111517 DUAL GATE STRUCTURE
Methods for forming a dual gate structure for a vertical TFT are described. The dual gate structure may be formed by performing a first etching process that...
2016/0111516 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
The present disclosure provides semiconductor devices and fabrication methods thereof. A stacked substrate includes an insulating layer between a substrate and...
2016/0111515 AIR GAP SPACER INTEGRATION FOR IMPROVED FIN DEVICE PERFORMANCE
A method for providing a FinFET device with an air gap spacer includes providing a substrate a plurality of fins and a dummy gate arranged transverse to the...
2016/0111514 ULTRA-LOW RESISTANCE GATE STRUCTURE FOR NON-PLANAR DEVICE VIA MINIMIZED WORK FUNCTION MATERIAL
A non-planar semiconductor structure includes an ultra-low resistance gate structure. The non-planar structure includes a semiconductor substrate and raised...
2016/0111513 MULTI-CHANNEL GATE-ALL-AROUND FET
A high performance GAA FET is described in which vertically stacked silicon nanowires carry substantially the same drive current as the fin in a conventional...
2016/0111512 LOWERING PARASITIC CAPACITANCE OF REPLACEMENT METAL GATE PROCESSES
The present disclosure provides a method of forming a gate structure of a semiconductor device with reduced gate-contact parasitic capacitance. In a...
2016/0111511 TRANSISTOR WITH PERFORMANCE BOOST BY EPITAXIAL LAYER
The present disclosure relates to a transistor device. In some embodiments, the transistor device has an epitaxial layer disposed over a substrate. The...
2016/0111510 SPLIT GATE FLASH MEMORY STRUCTURE WITH A DAMAGE FREE SELECT GATE AND A METHOD OF MAKING THE SPLIT GATE FLASH...
A method of manufacturing a split gate flash memory cell is provided. A select gate is formed on a semiconductor substrate. A sacrificial spacer is formed...
2016/0111509 METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE HAVING A DRAIN SIDE DUMMY CONTACT
A MOS transistor device includes a substrate including a gate formed thereon, and a spacer being formed on a sidewall of the gate; a source region and a drain...
2016/0111508 SEMICONDUCTOR DEVICE HAVING A TRENCH GATE AND METHOD FOR MANUFACTURING
A semiconductor device having a trench gate and method for manufacturing is disclosed. One embodiment includes a first semiconductor area and a second...
2016/0111507 ELECTRONIC DEVICE COMPRISING CONDUCTIVE REGIONS AND DUMMY REGIONS
A device includes an epitaxial region extending into a front surface of a chip. A portion of the chip adjacent the epitaxial region defines a collector. A gate...
2016/0111506 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device includes a first gate pattern and a second gate pattern on a substrate, the first gate pattern having a first height and the second gate...
2016/0111505 Semiconductor Device with Breakdown Preventing Layer
A semiconductor device with a breakdown preventing layer is provided. The breakdown preventing layer can be located in a high-voltage surface region of the...
2016/0111504 Semiconductor Device and Method of Manufacturing a Semiconductor Device Using an Alignment Layer
First trenches extend from a process surface into a semiconductor layer. An alignment layer with mask pits in a with respect to the process surface vertical...
2016/0111503 SEMICONDUCTOR DEVICE WITH IMPROVED FIELD PLATE
A transistor device includes a semiconductor body, a spacer layer, and a field plate. The spacer layer is over at least a portion of a surface of the...
2016/0111502 SEMICONDUCTOR DEVICE WITH IMPROVED FIELD PLATE
A transistor device includes a semiconductor body, a spacer layer, and a field plate. The spacer layer is over at least a portion of a surface of the...
2016/0111501 METHOD TO DEFINE THE ACTIVE REGION OF A TRANSISTOR EMPLOYING A GROUP III-V SEMICONDUCTOR MATERIAL
A group III-V transistor device employing a novel layout for isolating and/or defining the active region is provided. A group III-V heterojunction is arranged...
2016/0111500 TECHNIQUES FOR FORMING OPTOELECTRONIC DEVICES
Embodiments relate to use of a particle accelerator beam to form thin films of material from a bulk substrate are described. In particular embodiments, a bulk...
2016/0111499 SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
A MOSFET using a SiC substrate has a problem that a carbon-excess layer is formed on a surface by the application of mechanical stress due to thermal oxidation...
2016/0111498 Insulated Gate Bipolar Transistor Structure Having Low Substrate Leakage
A method of making a high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor...
2016/0111497 High-Voltage Normally-Off Field Effect Transistor With Channel Having Multiple Adjacent Sections
A device having a channel with multiple voltage thresholds is provided. The channel can include a first section located adjacent to a source electrode, which...
2016/0111496 Method and Structure for III-V FinFET
A method for fabricating a semiconductor device comprises forming a fin in a layer of III-V compound semiconductor material on a silicon-on-insulator...
2016/0111495 METHODS AND APPARATUS FOR FORMING HORIZONTAL GATE ALL AROUND DEVICE STRUCTURES
A method of forming a semiconductor device includes: forming a superlattice structure atop the top surface of a substrate, wherein the superlattice structure...
2016/0111494 NANOWIRE DEVICE WITH IMPROVED EPITAXY
As disclosed herein, a method for fabricating a nanowire device with improved epitaxy, includes forming a nanowire stack on a substrate, the nanowire stack...
2016/0111493 Double Trench Isolation
Isolation is provided by forming a first trench, depositing a cover layer on the bottom and sidewalls of the first trench, selectively removing the cover layer...
2016/0111492 Semiconductor Film with Adhesion Layer and Method for Forming the Same
Presented herein is a device including an insulator layer disposed over a substrate. An adhesion layer is disposed over the insulator layer and includes a...
2016/0111491 FIN DEVICE WITH BLOCKING LAYER IN CHANNEL REGION
A semiconductor device includes a fin defined on a substrate and a gate electrode structure formed above the fin. A channel region of the device is defined...
2016/0111490 INSULATED GATE TYPE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate,...
2016/0111489 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A p anode layer is formed on one main surface of an n.sup.- drift layer. N.sup.+ cathode layer having an impurity concentration more than that of the n.sup.-...
2016/0111488 INTEGRATED CIRCUITS WITH LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR STRUCTURES AND METHODS FOR FABRICATING...
Integrated circuits with improved laterally diffused metal oxide semiconductor (LDMOS) structures, and methods of fabricating the same, are provided. An...
2016/0111487 ORGANIC LIGHT-EMITTING DISPLAY APPARATUS
A display apparatus has pixel area to emit light, a transmission area to transmit external light, and wirings including scan wiring, data wiring, and power...
2016/0111486 DISPLAY DEVICE
A display device includes contact holes opened in an insulating film outside of a display area in which pixels are arranged, and having a conductive film...
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