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Patent # Description
2016/0111435 THREE-DIMENSIONAL MEMORY STRUCTURE HAVING SELF-ALIGNED DRAIN REGIONS AND METHODS OF MAKING THEREOF
A memory stack structure can be formed through a stack of an alternating plurality of first material layers and second material layers and through an overlying...
2016/0111434 THREE DIMENSIONAL NAND STRING MEMORY DEVICES AND METHODS OF FABRICATION THEREOF
Monolithic three-dimensional NAND memory strings and methods of fabricating a monolithic three-dimensional NAND memory string include forming single crystal or...
2016/0111433 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device may include a dummy structure formed on a peripheral...
2016/0111432 SINGLE-SEMICONDUCTOR-LAYER CHANNEL IN A MEMORY OPENING FOR A THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE
A memory film layer is formed in a memory opening through an alternating stack of first material layers and second material layers. A sacrificial material...
2016/0111431 SEMICONDUCTOR DEVICE
Provided is a semiconductor device. The semiconductor device includes a conductive pattern disposed on a semiconductor substrate. First and second conductive...
2016/0111430 CONTACT FOR SEMICONDUCTOR FABRICATION
A semiconductor device includes a substrate, a fin structure on the substrate, the fin structure comprising a doped region, a first gate over the fin...
2016/0111429 LC MODULE LAYOUT ARRANGEMENT FOR CONTACT OPENING ETCH WINDOWS
A lay-out arrangement for LC modules in 3D semiconductor memories is described that avoids large step height. The arrangement creates insulating/conducting...
2016/0111428 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active...
2016/0111427 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
A semiconductor device includes a first and second fin-shaped semiconductor layers on a substrate. A first insulating film is around the first and second...
2016/0111426 METHODS OF INTEGRATING MULTIPLE GATE DIELECTRIC TRANSISTORS ON A TRI-GATE (FINFET) PROCESS
Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for...
2016/0111425 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
The present disclosure provides a semiconductor structure includes a semiconductor layer having a first and a second surface, and an interlayer dielectric...
2016/0111424 Multi-Voltage Complementary Metal Oxide Semiconductor Integrated Circuits Based On Always-On N-Well Architecture
Examples of multi-voltage (MV) complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) based on always-on N-well architecture are described. A...
2016/0111423 EXTREME HIGH MOBILITY CMOS LOGIC
A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS...
2016/0111422 METHOD FOR MAKING HIGH VOLTAGE INTEGRATED CIRCUIT DEVICES IN A FIN-TYPE PROCESS AND RESULTING DEVICES
Methods for making high voltage IC devices utilizing a fin-type process and resulting devices are disclosed. Embodiments include forming two pluralities of...
2016/0111421 MULTIPLE CPP FOR INCREASED SOURCE/DRAIN AREA FOR FETS INCLUDING IN A CRITICAL SPEED PATH
An integrated circuit comprises at least one block comprising a first cell and a second cell. The first cell comprises a first FET formed with a first...
2016/0111420 FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE AND METHOD FOR FORMING THE SAME
A fin field effect transistor (FinFET) device structure and method for forming the FinFET device structure are provided. The FinFET structure includes a...
2016/0111419 SEMICONDUCTOR DEVICE
In order to realize an SJ-MOSFET and an IGBT on a single chip and realize a new arrangement configuration for an SJ-MOSFET section and an IGBT section in a...
2016/0111418 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device includes a semiconductor substrate, a transistor, a conductive contact and a capacitor. The transistor is formed on the semiconductor...
2016/0111417 ELECTRONIC CIRCUITS INCLUDING A MOSFET AND A DUAL-GATE JFET
Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a...
2016/0111416 INTEGRATED CIRCUIT WITH MATCHING THRESHOLD VOLTAGES AND METHOD FOR MAKING SAME
An integrated circuit having a substrate, a buffer layer formed over the substrate, a barrier layer formed over the buffer layer, and an isolation region that...
2016/0111415 Insulated Gate Bipolar Transistor Comprising Negative Temperature Coefficient Thermistor
An embodiment of an IGBT comprises an emitter terminal at a first surface of a semiconductor body. The IGBT further comprises a collector terminal at a second...
2016/0111414 SCR WITH FIN BODY REGIONS FOR ESD PROTECTION
An electrostatic discharge protection circuit is disclosed. A method of manufacturing a semiconductor structure includes forming a semiconductor controlled...
2016/0111413 Avalanche Diode Having an Enhanced Defect Concentration Level and Method of Making the Same
The invention relates to an avalanche diode that can be employed as an ESD protection device. An avalanche ignition region is formed at the p-n junction of the...
2016/0111412 ESD PROTECTION CIRCUIT
An electrostatic discharge (ESD) protection circuit may include an n-channel metal oxide semiconductor (NMOS) having a drain connected to a power terminal and...
2016/0111411 STRUCTURE AND METHOD FOR ENHANCING ROBUSTNESS OF ESD DEVICE
A method and structure of improving the robustness of an electrostatic discharge (ESD) protection device is disclosed. One aspect of the instant disclosure...
2016/0111410 Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect
A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of...
2016/0111409 3D Packages and Methods for Forming the Same
Embodiments of the present disclosure include a semiconductor device, a package and methods of forming a semiconductor device and a package. An embodiment is a...
2016/0111408 LIGHT EMITTING DIODES AND A METHOD OF PACKAGING THE SAME
Disclosed herein is a method of assembling an array of light emitting diode (LED) dies on a substrate comprising: positioning dies in fluid; exposing the dies...
2016/0111407 METHOD AND SYSTEM FOR TEMPLATE ASSISTED WAFER BONDING USING PEDESTALS
A multilayer semiconductor has stacks of composite semiconductor materials. Multiple composite devices are bonded on a silicon-on-insulator wafer forming an...
2016/0111406 TOP-SIDE INTERCONNECTION SUBSTRATE FOR DIE-TO-DIE INTERCONNECTION
At least one method, apparatus and system disclosed involves a multi-die integrated circuit device. A first substrate portion having a first height is formed....
2016/0111405 METHOD FOR INTEGRATING A LIGHT EMITTING DEVICE
Light emitting devices and methods of integrating micro LED devices into light emitting device are described. In an embodiment a light emitting device includes...
2016/0111404 METHODS OF FORMING 3-D CIRCUITS WITH INTEGRATED PASSIVE DEVICES
Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrates-vias...
2016/0111403 LEADFRAME-BASED SYSTEM-IN-PACKAGES HAVING SIDEWALL-MOUNTED SURFACE MOUNT DEVICES AND METHODS FOR THE PRODUCTION...
Embodiments of a method for fabricating System-in-Packages (SiPs) are provided, as are embodiments of a SiP. In one embodiment, the method includes producing a...
2016/0111402 LIGHT EMITTING DEVICE
There is presented a light emitting device, having plural light emitting elements disposed on a substrate, in which a protection element, such as a zener...
2016/0111401 ILLUMINATION ASSEMBLY, METHOD OF MANUFACTURING THE ILLUMINATION ASSEMBLY, AND BACKLIGHT MODULE INCLUDING THE...
An illumination assembly includes a substrate, a wiring structure, a reflecting layer and a plurality of light-emitting diodes. The wiring structure is formed...
2016/0111400 LIGHT EMITTING DEVICE
A flip chip light emitting diode includes a plurality of light emitting diodes and an encapsulation covering the plurality of light emitting diodes. Each of...
2016/0111399 SEMICONDUCTOR SYSTEM HAVING SEMICONDUCTOR APPARATUS AND METHOD OF DETERMINING DELAY AMOUNT USING THE...
A semiconductor apparatus includes: a slave chip including a signal transfer unit configured to determine whether or not to transfer an input signal in...
2016/0111398 Semiconductor Device with Discrete Blocks
A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having...
2016/0111397 SEMICONDUCTOR CHIP AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME
A semiconductor chip includes a substrate, through-electrodes passing through the substrate, and a dielectric layer formed between the substrate and the...
2016/0111396 SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
A method of fabricating a package-on-package (PoP) type of semiconductor package may include providing a lower package with a lower substrate, a lower...
2016/0111395 METHOD OF FORMING A CHIP ASSEMBLY AND CHIP ASSEMBLY
A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in...
2016/0111394 METHOD FOR PERMANENT BONDING OF WAFERS
A method for bonding of a first contact surface of a first substrate to a second contact surface of a second substrate according to the following steps:...
2016/0111393 Solderless Mounting for Semiconductor Lasers
A first contact surface of a semiconductor laser chip can be formed to a first target surface roughness and a second contact surface of a carrier mounting can...
2016/0111392 Method and Apparatus for Connecting Packages onto Printed Circuit Boards
Methods and apparatus are disclosed for attaching the integrated circuit (IC) packages to printed circuit boards (PCBs) to form smooth solder joints. A polymer...
2016/0111391 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
Provided are a semiconductor device and a method of manufacturing the same. A carrier is removed after a first semiconductor die and a second semiconductor die...
2016/0111390 METHOD FOR MANUFACTURING ELECTRONIC DEVICES
An embodiment for manufacturing electronic devices is proposed. The embodiment includes the following phases: a) forming a plurality of chips in a...
2016/0111389 BONDING WIRE FOR SEMICONDUCTOR DEVICE USE AND METHOD OF PRODUCTION OF SAME
Bonding wire for semiconductor device use where both leaning failures and spring failures are suppressed by (1) in a cross-section containing the wire center...
2016/0111388 SEMICONDUCTOR DEVICE
A technique capable of improving reliability of a semiconductor device is provided. In the present invention, as a wiring board on which a semiconductor chip...
2016/0111387 PLANARITY-TOLERANT REWORKABLE INTERCONNECT WITH INTEGRATED TESTING
A structure includes an electrical interconnection between a first substrate including a plurality of protrusions and a second substrate including a plurality...
2016/0111386 BOND PAD STRUCTURE FOR LOW TEMPERATURE FLIP CHIP BONDING
Methods for preparing 3D integrated semiconductor devices and the resulting devices are disclosed. Embodiments include forming a first and a second bond pad on...
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