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PACKAGE ON PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
The described embodiments of mechanisms of forming a package on package (PoP) structure involve bonding with connectors with non-solder metal balls to a...
SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor package structure includes a first semiconductor substrate including a conductive pad; and a conductive pillar on the conductive pad and...
METHOD OF USING ALUMINUM LAYER AS ETCHING STOP LAYER FOR PATTERNING A
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a dielectric layer; forming an...
VERTICAL BREAKDOWN PROTECTION LAYER
The present disclosure relates to a semiconductor structure including a plurality of connecting lines arranged on a plurality of vertical levels, the plurality...
SEMICONDUCTOR STRUCTURE INCLUDING A DIE SEAL LEAKAGE DETECTION MATERIAL,
METHOD FOR THE FORMATION THEREOF AND...
A semiconductor structure includes a semiconductor substrate, one or more interconnect layers provided over the substrate and a circuit. The circuit includes a...
NEW STRUCTURE OF MICROELECTRONIC PACKAGES WITH EDGE PROTECTION BY COATING
Disclosed herein are edge-coated microelectronic packages comprising a microelectronic package having a top, a bottom, and an exposed edge, and a coating...
A semiconductor device includes a semiconductor element having a lower surface bonded to an insulating substrate side, and a plate-shaped lead terminal bonded...
SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD OF THE SAME
The present disclosure provides a method for manufacturing a semiconductor package. The method includes (1) determining a die warpage value under a...
Molded Device with Anti-delamination Structure Providing Multi-layered
The present invention provides a molded encapsulated multi-layered semiconductor device, comprising a first substrate, a second substrate and an...
A semiconductor package including a semiconductor chip having an active surface and a non-active surface opposite to the active surface, a ground member...
TEMPORARY BONDING OF PACKAGES TO CARRIER FOR DEPOSITING METAL LAYER FOR
Techniques for batch processing LGA and BGA packages for forming a very thin conformal metal film over the packages are described. An array of the packages is...
LOW ENERGY ETCH PROCESS FOR NITROGEN-CONTAINING DIELECTRIC LAYER
A stack that includes, from bottom to top, a nitrogen-containing dielectric layer, an interconnect level dielectric material layer, and a hard mask layer is...
MULTI-LAYER DIELECTRIC STACK FOR PLASMA DAMAGE PROTECTION
Embodiments of the disclosure generally provide multi-layer dielectric stack configurations that are resistant to plasma damage. Methods are disclosed for the...
LOW CAPACITANCE INTERCONNECT STRUCTURES AND ASSOCIATED SYSTEMS AND METHODS
Semiconductor device interconnect structures having low capacitance and associated systems and methods are disclosed herein. In one embodiment, a method of...
STRUCTURE AND FORMATION METHOD OF DAMASCENE STRUCTURE
A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a first conductive...
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device includes a substrate having an active region, a first gate structure over a top surface of the substrate, a second gate structure over...
NOVEL SEMICONDUCTOR SYSTEM AND DEVICE
A 3D IC device including: a first semiconductor layer including first mono-crystallized transistors, where the first mono-crystallized transistors are...
SEMICONDUCTOR STRUCTURES AND FABRICATION METHOD THEREOF
A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate; forming an initial metal layer;...
POWER SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING THE SAME
A power semiconductor module may include a first device and a second device spaced apart from the first device at a predetermined interval. A first assembling...
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME
A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate having a trench, a stacked strip...
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device has a resistor area and wiring area selectively disposed on a semiconductor substrate. In this semiconductor device, a second interlayer...
CHIP PACKAGE STRUCTURE
A chip package structure is provided. The chip package structure includes a chip, at least one inducting coil, a molding compound and a redistribution circuit...
Electrical Connections for Chip Scale Packaging
Electrical connections for chip scale packaging are disclosed. In one embodiment, a semiconductor device includes a post-passivation layer disposed over a...
One semiconductor device includes one parallel transistor for connecting in parallel multiple vertical transistors disposed in an active region on a...
3D NONVOLATILE MEMORY DEVICE
A 3D nonvolatile memory device including memory cells vertically stacked is disclosed. Word lines are integrally formed to be elongated over adjacent cell...
DUMMY METAL STRUCTURE AND METHOD OF FORMING DUMMY METAL STRUCTURE
Methods for forming a dummy metal structure between dies on a semiconductor wafer and the resulting devices are disclosed. Embodiments may include forming...
ELECTRONIC PACKAGE AND FABRICATION METHOD THEREOF
A method for fabricating an electronic package is provided, which includes the steps of: providing an insulating layer having at least an electronic element...
A semiconductor package is provided. In one configuration, the semiconductor package includes a substrate. First and second conductive traces are disposed on...
A semiconductor device has a chip mounting part, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip is mounted over the...
Compact Multi-Die Power Semiconductor Package
One disclosed implementation is a power semiconductor package including a sync transistor having a drain on its top surface and a source and a gate on its...
Compact Single-Die Power Semiconductor Package
Disclosed is a power semiconductor package including a power transistor having a first power electrode and a gate electrode on its top surface and a second...
ELECTRONIC DEVICE WITH FIRST AND SECOND CONTACT PADS AND RELATED METHODS
An electronic device may include leads, an IC having first and second bond pads, and an encapsulation material adjacent the leads and the IC so the leads...
EMBEDDING THIN CHIPS IN POLYMER
Systems and methods are provided for the embedding of thin chips. A well region is generated in a substrate that includes a conductive material disposed on a...
DIELECTRIC COVER FOR A THROUGH SILICON VIA
An approach to creating a semiconductor structure for a dielectric layer over a void area includes determining a location of a void area of the topographical...
SOLUTION FOR TSV SUBSTRATE LEAKAGE
A semiconductor device manufacturing method includes providing a wafer, which includes a semiconductor substrate, a semiconductor device located on the...
Methods of Cooling Packaged Semiconductor Devices
Packages for semiconductor devices, packaged semiconductor devices, and methods of cooling packaged semiconductor devices are disclosed. In some embodiments, a...
PACKAGED SEMICONDUCTOR DEVICES
A semiconductor device has a semiconductor chip having a first surface with metallized terminals and a parallel second surface. A frame of insulating material...
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device includes: an interlayer insulating film covering: a cathode region and an anode region to form a pn junction with each other; a cathode...
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
Provided are a semiconductor package and a method of fabricating the same. The package substrate includes a hole, which may be used to form a mold layer...
Semiconductor Component Having Inner and Outer Semiconductor Component
A semiconductor component includes an inner semiconductor component housing and an outer semiconductor component housing. The inner semiconductor component...
SEMICONDUCTOR MODULE, SEMICONDUCTOR DEVICE, AND VEHICLE
A base plate (1) includes a fixed surface and a radiating surface which is a surface opposite to the fixed surface. An insulating substrate (3) is bonded to...
METHOD AND APPARATUS FOR CHARACTERIZING METAL OXIDE REDUCTION
Method and apparatus for characterizing metal oxide reduction using metal oxide films formed in an anneal chamber are disclosed. Oxygen is provided into an...
METHOD OF FABRICATING FLASH MEMORY
A method of fabricating a flash memory includes providing a fin structure. The fin structure includes a floating gate material, an oxide layer and a...
METHOD AND APPARATUS FOR CHARACTERIZING METAL OXIDE REDUCTION
Method and apparatus for characterizing metal oxide reduction using metal oxide films formed by exposure to an oxygen plasma are disclosed. A substrate...
METHOD OF UTILIZING TRENCH SILICIDE IN A GATE CROSS-COUPLE CONSTRUCT
A method of forming a logic cell utilizing a TS gate cross-couple construct and the resulting device are provided. Embodiments include forming active fins and...
SEMICONDUCTOR DEVICE INCLUDING GATE CHANNEL HAVING ADJUSTED THRESHOLD
A semiconductor device includes at least one first semiconductor fin formed on an nFET region of a semiconductor device and at least one second semiconductor...
CONTACT LINERS FOR INTEGRATED CIRCUITS AND FABRICATION METHODS THEREOF
Contact liners for integrated circuits and fabrication methods thereof are presented. The methods include: fabricating an integrated circuit structure having a...
METHOD TO CO-INTEGRATE SiGe AND Si CHANNELS FOR FINFET DEVICES
A method for co-integrating finFETs of two semiconductor material types, e.g., Si and SiGe, on a bulk substrate is described. Fins for finFETs may be formed in...
STRAINED STACKED NANOSHEET FETS AND/OR QUANTUM WELL STACKED NANOSHEET
Exemplary embodiments provide for fabricating a biaxially strained nanosheet. Aspects of the exemplary embodiments include: growing an epitaxial crystalline...
Method and Structure for FinFET Isolation
A semiconductor device with effective FinFET isolation and method of forming the same are disclosed. The method includes receiving a substrate having an active...