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Patent # Description
2016/0111184 COATED STEEL WIRE AS ARMOURING WIRE FOR POWER CABLE
A steel wire as an armoring wire for a power cable for transmitting electrical power, where the steel wire has a steel core and a non-magnetic coating. The...
2016/0111183 Composite Wrapped Steel Tubes for Use in Umbilicals
Umbilicals may contain one or more steel tubes as well as low and medium voltage electricals and/or fillers, where one or more of the steel tubes comprise both...
2016/0111182 ELECTRICAL STEEL SHEET PROVIDED WITH INSULATING COATING
There is provided an electrical steel sheet provided with an insulating coating which has high corrosion resistance and high adhesion. The electrical steel...
2016/0111181 ANISOTROPIC ELECTROCONDUCTIVE PARTICLES
An anisotropic electroconductive particle including a first insulating layer, a first conductive layer disposed on the first insulating layer, and a second...
2016/0111180 METHOD OF FORMING AMORPHOUS CARBON MONOLAYER AND ELECTRONIC DEVICE INCLUDING AMORPHOUS CARBON MONOLAYER
A method of forming an amorphous carbon monolayer (ACM) and an electronic device including the ACM are provided. The method includes forming the ACM on a...
2016/0111179 COPPER ALLOY FOR ELECTRIC AND ELECTRONIC DEVICE, COPPER ALLOY SHEET FOR ELECTRIC AND ELECTRONIC DEVICE,...
A copper alloy for electric and electronic devices includes: Zn from more than 2 mass % to less than 23 mass %; Sn at 0.1 mass % or more and 0.9 mass % or...
2016/0111178 COMPOSITE FILAR FOR IMPLANTABLE MEDICAL DEVICE
A composite filar has a conductive core, an outer fatigue-resistant metallic layer and a diffusion barrier between the core and the fatigue-resistant layer to...
2016/0111177 X-RAY SOURCE
An X-ray source comprising: an elongate tubular housing adapted to be fitted into a port of and extend into a chamber containing a sample to be analysed,...
2016/0111176 PRODUCTION OF ISOTOPES USING HIGH POWER PROTON BEAMS
The invention provides for a method for producing isotopes using a beam of particles from an accelerator, whereby the beam is maintained at between about 70 to...
2016/0111175 MECHANICAL COMPONENT
This disclosure concerns reducing or elimination the build-up of coolant materials in the fuel handling and component maintenance systems of nuclear reactors,...
2016/0111174 ADVANCED FIRST CORE FUEL ASSEMBLY CONFIGURATION
An advanced initial core fuel configuration is for improving the fuel management efficiency and thus economics for a nuclear reactor. The advanced initial core...
2016/0111173 GAMMA-RAY SENSING PROBE USING CERENKOV EFFECT AND SYSTEM FOR IDENTIFYING BURNUP OF SPENT NUCLEAR FUEL ASSEMBLY...
Provided are a gamma-ray sensing probe using the Cerenkov effect, and a system for identifying the burnup of a spent nuclear fuel assembly using the gamma-ray...
2016/0111172 SEMICONDUCTOR DEVICE
A semiconductor device includes: a plurality of repair fuse circuits configured to each program a repair target address; and an enable signal generation...
2016/0111171 MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
A memory device may include an address latch circuit that latches an address received from an exterior of the memory device, a repair signal generation circuit...
2016/0111170 METHOD AND APPARATUS FOR TESTING MEMORY
In an integrated circuit, a first scan chain of flip-flops is loaded with data for testing data retention of the flip-flops and a memory is loaded with data...
2016/0111169 MEMORY TEST APPARATUS
A memory test apparatus includes a test board unit including a first test board configured to load for testing a first memory system including a plurality of...
2016/0111168 MEMORY CIRCUIT HAVING NON-VOLATILE MEMORY CELL AND METHODS OF USING
One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a...
2016/0111167 APPARATUSES AND METHODS FOR REDUCING READ DISTURB
Apparatuses and methods for reducing read disturb are described herein. An example apparatus may include a first memory subblock including a first select gate...
2016/0111166 Simultaneous Programming of Many Bits in Flash Memory
A semiconductor device includes: a plurality of memory cells; a plurality of local bit lines connected to respective memory cells of the plurality of memory...
2016/0111165 METHODS OF OPERATING A NONVOLATILE MEMORY DEVICE
An operating method of a nonvolatile memory device is provided which sequentially performs a plurality of erase loops to erase at least one of a plurality of...
2016/0111164 Weak Erase After Programming To Improve Data Retention In Charge-Trapping Memory
Techniques are provided to improve long term data retention in a charge-trapping memory device. In addition to a primary charge-trapping layer in which most...
2016/0111163 PARALLEL PROGRAMMING OF NONVOLATILE MEMORY CELLS
Adaptive write operations for non-volatile memories select programming parameters according to monitored programming performance of individual memory cells. In...
2016/0111162 NOVEL NAND ARRAY ARCHITECTURE FOR MULTIPLE SIMUTANEOUS PROGRAM AND READ
This invention discloses a HiNAND array scheme with multiple-level of bit lines (BLs) including metal3 global bit lines (GBLs), divided metal2 Segment bit...
2016/0111161 BIASING OF UNSELECTED BLOCKS OF NON-VOLATILE MEMORY TO REDUCE LOADING
Techniques are presented for reducing the loading on the source lines for NAND type memories that decode memory blocks in multi-block groups, an example 3D...
2016/0111160 APPARATUSES AND METHODS FOR SEGMENTED SGS LINES
Apparatuses and methods for segmented SGS lines are described. An example apparatus ma include first and second pluralities of memory subblocks of a memory...
2016/0111159 10T Non-Volatile Static Random-Access Memory
A memory including an array of nvSRAM cells and method of operating the same are provided. Each nvSRAM cell includes a volatile charge storage circuit, and a...
2016/0111158 Semiconductor Memory Having Volatile and Multi-Bit Non-Volatile Functionality and Method of Operating
A semiconductor memory cell, semiconductor memory devices comprising a plurality of the semiconductor memory cells, and methods of using the semiconductor...
2016/0111157 METHOD FOR READING A THIRD-DIMENSIONAL EMBEDDED RE-WRITEABLE NON-VOLATILE MEMORY AND REGISTERS
A non-volatile register includes register logic connected with first and second ends of a memory element. The register logic is positioned below the memory...
2016/0111156 MEMORY CIRCUIT AND METHOD OF PROGRAMMING MEMORY CIRCUIT
A method includes applying a first voltage setting to a memory cell for a first period of time in response to a command for programming a first logical state...
2016/0111155 NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND REWRITING METHOD THEREOF
A bitwise bidirectionally rewritable nonvolatile semiconductor storage device capable of performing a high-speed data rewrite, while enhancing endurance...
2016/0111154 NON-VOLATILE, PIEZOELECTRONIC MEMORY BASED ON PIEZORESISTIVE STRAIN PRODUCED BY PIEZOELECTRIC REMANENCE
A nonvolatile memory storage device includes a ferroelectric (FE) material coupled with a piezoresistive (PR) material through an inherent piezoelectric...
2016/0111153 METHOD FOR PROGRAMMING SWITCHING ELEMENT
In order to realize a switching element that is highly reliable and can be highly integrated, in a method for programming a switching element of the present...
2016/0111152 METHOD FOR CAPACITIVELY READING RESISTIVE MEMORY ELEMENTS AND NONVOLATILE, CAPACITIVELY READABLE MEMORY...
A method for reading out a non-volatile memory element having at least two stable states 0 and 1. This memory element comprises at least one resistive memory...
2016/0111151 RESISTANCE VARIABLE MEMORY APPARATUS, READ/WRITE CIRCUIT UNIT AND OPERATION METHOD THEREOF
A resistance variable memory apparatus may include a memory cell array. The resistance variable memory apparatus may include a read/write circuit unit. The...
2016/0111150 DUAL POLARITY READ OPERATION
A data storage device includes a memory die and a controller coupled to the memory die. The memory die includes a resistive memory and read/write circuitry...
2016/0111149 ADAPTIVE RESISTIVE DEVICE AND METHODS THEREOF
A system that incorporates teachings of the subject disclosure may include, for example, a device including a nanoelectrode having a gap, and a resistive...
2016/0111148 READING A MULTI-BIT VALUE FROM A MEMORY CELL
Adaptive write operations for non-volatile memories select programming parameters according to monitored programming performance of individual memory cells. In...
2016/0111147 Non-Volatile Semiconductor Memory Adapted to Store a Multi-Valued Data in a Single Memory Cell
A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data...
2016/0111146 CELL STRUCTURE OF RANDOM ACCESS MEMORY, RANDOM ACCESS MEMORY AND OPERATION METHODS
The present disclosure provides a cell structure, a random access memory and operation methods. The cell structure with four transistors, including a first...
2016/0111145 6T SRAM CELL
A 6T SRAM cell includes a write inverter which includes a write pull-up transistor and a write pull-down transistor, a read inverter which includes a read...
2016/0111144 PULSE WIDTH MODULATION DEVICE
A pulse width modulation device for use in an N-ports random access memory having a plurality of word line sets, wherein a specified word line set comprises N...
2016/0111143 STATIC RANDOM ACCESS MEMORY AND METHOD OF CONTROLLING THE SAME
A static random access memory (SRAM) including at least a first memory cell array, a second memory cell array, a first data line connected to the first memory...
2016/0111142 MEMORY WITH BIT LINE CONTROL
A memory comprises a first set of memory cells coupled between a first data line and a second data line. The memory also includes a first input/output (I/O)...
2016/0111141 SEMICONDUCTOR STORAGE DEVICE
A semiconductor storage device including a first power supply line; a second power supply line; a first bit line; a second bit line; a first load transistor...
2016/0111140 SEMICONDUCTOR DEVICE AND METHOD OF DRIVING THE SAME
A semiconductor device includes a 1st controller suitable for generating refresh control signals for controlling two or more types of refresh operations...
2016/0111139 DYNAMIC SELECTION OF OUTPUT DELAY IN A MEMORY CONTROL DEVICE
In an example, a memory control device includes an output circuit, an output delay unit, and a write-levelization controller. The output circuit is coupled to...
2016/0111138 SEMICONDUCTOR MEMORY DEVICE
Proposed as a configuration, a controlling method, and a testing method for a ferroelectric shadow memory are (1) a bit line non-precharge method, in which no...
2016/0111137 Addressing, Command Protocol, and Electrical Interface for Non-volatile Memories Utilized in Recording Usage Counts
A memory module, including a plurality of memory cells and a plurality of signal lines for communicating with a processing device. The memory module is...
2016/0111136 ADDRESS DECODING CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME
An address decoding circuit may include a main address processing block configured to latch a main address, and output a latched main address. The address...
2016/0111135 INPUT/OUTPUT STROBE PULSE CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME
An input/output strobe pulse control circuit includes a control signal generator suitable for generating first to third control signals in response to a column...
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