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Patent # Description
2016/0118390 Structure and Method for FinFET SRAM
Provided is an embedded FinFET SRAM structure and methods of making the same. The embedded FinFET SRAM structure includes an array of SRAM cells. The SRAM...
2016/0118389 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device having a high degree of freedom of layout has a first part AR1, in which a plurality of p-type wells PW and n-type wells NW are...
2016/0118388 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A first space partitioned by first and second line patters (52, 53) is filled with a multilayer film that is composed of a first silicon film (55) having a...
2016/0118387 SEMICONDUCTOR DEVICE WITH A BURIED OXIDE STACK FOR DUAL CHANNEL REGIONS AND ASSOCIATED METHODS
A method for making a semiconductor device includes forming a buried oxide stack on a semiconductor wafer. The buried oxide stack includes a first oxide layer,...
2016/0118386 SEMICONDUCTOR STRUCTURE HAVING FINFET ULTRA THIN BODY AND METHODS OF FABRICATION THEREOF
In one aspect there is set forth herein a semiconductor structure having fins extending upwardly from an ultrathin body (UTB). In one embodiment a multilayer...
2016/0118385 REPLACEMENT GATE STRUCTURES FOR TRANSISTOR DEVICES
A transistor device includes a gate structure positioned above a semiconductor substrate and spaced-apart sidewall spacers positioned above the substrate and...
2016/0118384 SELF-ALIGNED CONTACT METALLIZATION FOR REDUCED CONTACT RESISTANCE
Techniques are disclosed for forming low contact resistance transistor devices. A p-type germanium layer is provided between p-type source/drain regions and...
2016/0118383 SEMICONDUCTOR DEVICE
A semiconductor device includes an antenna functioning as a coil, a capacitor electrically connected to the antenna in parallel, a passive element forming a...
2016/0118382 Method of Manufacturing a Reverse Blocking Semiconductor Device
A reverse blocking semiconductor device is manufactured by introducing impurities of a first conductivity type into a semiconductor substrate of the first...
2016/0118381 HYBRID WIDE-BANDGAP SEMICONDUCTOR BIPOLAR SWITCHES
A hybrid semiconductor bipolar switch in which a normally-on high-voltage wide-bandgap semiconductor bipolar switch and a normally-off field effect transistor...
2016/0118380 INTEGRATED SNUBBER IN A SINGLE POLY MOSFET
Aspects of the present disclosure describe MOSFET devices that have snubber circuits. The snubber circuits comprise one or more resistors with a dynamically...
2016/0118379 CASCODE SEMICONDUCTOR DEVICE STRUCTURE AND METHOD THEREFOR
In one embodiment, a cascode rectifier structure includes a group III-V semiconductor structure includes a heterostructure disposed on a semiconductor...
2016/0118378 SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME AND STRUCTURE FOR SUPPRESSING CURRENT LEAKAGE
A structure for suppressing current leakage and a semiconductor device including the same are provided. The structure for suppressing current leakage includes...
2016/0118377 METHOD OF FORMING A HIGH ELECTRON MOBILITY SEMICONDUCTOR DEVICE AND STRUCTURE THEREFOR
In one embodiment, a method of forming a semiconductor device can comprise; forming a HEM device on a semiconductor substrate. The semiconductor substrate...
2016/0118376 SEMICONDUCTOR INTEGRATED CIRCUIT
A first power line configured to receive a first voltage, a second power line configured to receive a second voltage which is lower than the first voltage, a...
2016/0118375 SEMICONDUCTOR INTEGRATED CIRCUIT
A first power line configured to receive a first voltage, a second power line configured to receive a second voltage which is lower than the first voltage, a...
2016/0118374 ELECTROSTATIC DISCHARGE PROTECTION STRUCTURE CAPABLE OF PREVENTING LATCH-UP ISSUE CAUSED BY UNEXPECTED NOISE
An electrostatic discharge protection structure comprises an isolation layer, a high voltage P-well, an N-well, a P-well, a first doped region of N-type...
2016/0118373 MULTIPLE DIE LEAD FRAME PACKAGING
First and second semiconductor die are mounted to first and second die pads of a lead frame disposed in a lead frame sheet. With a plurality of wire bonds,...
2016/0118372 MECHANISMS FOR FORMING PACKAGE STRUCTURE
A method for forming a package structure is provided. The method includes forming a plurality of conductive columns over a carrier substrate and forming an...
2016/0118371 SEMICONDUCTOR PACKAGE
A semiconductor package includes a package substrate, a first semiconductor chip having a plurality of first connection terminals disposed on a bottom surface...
2016/0118370 DISPLAY DEVICE
A display device is disclosed, which comprises: a first substrate; a second substrate disposed adjacent to the first substrate and partially covering the first...
2016/0118369 Package-on-Package Structure with Through Molding Via
Disclosed herein is a device comprising a first package having a first side with a plurality of connectors disposed thereon and a second package mounted on the...
2016/0118368 SEMICONDUCTOR DEVICE
A semiconductor device includes a first semiconductor chip that includes a first main surface, a first inductor formed on the first main surface, and a first...
2016/0118367 REDISTRIBUTION LAYERS FOR MICROFEATURE WORKPIECES, AND ASSOCIATED SYSTEMS AND METHODS
Redistribution layers for microfeature workpieces, and associated systems and methods are disclosed. One method for processing a microfeature workpiece system...
2016/0118366 Semiconductor Packages Including Heat Dissipation Parts
A semiconductor package includes a lower package with a lower substrate and a lower semiconductor chip. A heat dissipation part is provided adjacent to a side...
2016/0118365 DIE ATTACHMENT FOR PACKAGED SEMICONDUCTOR DEVICE
A method for forming a packaged semiconductor device includes attaching a first major surface of a semiconductor die to a plurality of protrusions extending...
2016/0118364 Integrated Circuit with a Thermally Conductive Underfill and Methods of Forming Same
An integrated circuit includes a substrate and at least one chip. Each chip is disposed over the substrate or the other chip. Solder bumps are disposed between...
2016/0118363 BONDING STAGE AND METHOD OF MANUFACTURING THE SAME
Provided is a bonding stage including: a rigid block (10) having a plurality of projections (11) on a surface (16) of the base body, upper surfaces of the...
2016/0118362 BONDING APPARATUS AND SUBSTRATE MANUFACTURING EQUIPMENT INCLUDING THE SAME
A bonding apparatus of substrate manufacturing equipment includes an upper stage, a lower stage facing the upper stage and which is configure and dedicated to...
2016/0118361 INTEGRATED CIRCUIT PACKAGE STRUCTURE AND INTERFACE AND CONDUCTIVE CONNECTOR ELEMENT FOR USE WITH SAME
Consistent with the present disclosure, a conductive connector element for use with a rigid or flexible insulating substrate to electrically couple first and...
2016/0118360 Bump-on-Trace Design for Enlarge Bump-to-Trace Distance
A package includes a first and a second package component. The first package component includes a first metal trace and a second metal trace at the surface of...
2016/0118359 Interconnect Structures and Methods of Forming Same
Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is an interconnect...
2016/0118358 DIRECT INJECTION MOLDED SOLDER PROCESS FOR FORMING SOLDER BUMPS ON WAFERS
Solder bumps are provided on round wafers through the use of injection molded solder. Copper pillars or ball limiting metallurgy are formed over I/O pads...
2016/0118357 PACKAGED SEMICONDUCTOR DEVICE WITH INTERIOR POLYGONAL PADS
Embodiments of a packaged semiconductor device with interior polygon pads are disclosed. One embodiment includes a semiconductor chip and a package structure...
2016/0118356 Interconnect Structure and Method of Forming Same
An apparatus comprises a dielectric layer formed on a first side of a substrate, a first side interconnect structure comprising a first metal line and a pad...
2016/0118355 PLANAR PASSIVATION FOR PADS
Devices and methods for forming a device are presented. The method includes providing a substrate having circuit component and a dielectric layer over the...
2016/0118354 MICROELECTRONIC PACKAGE UTILIZING MULTIPLE BUMPLESS BUILD-UP STRUCTURES AND THROUGH-SILICON VIAS
A microelectronic package having a first bumpless build-up layer structure adjacent an active surface and sides of a microelectronic device and a second...
2016/0118353 Systems and Methods Using an RF Circuit on Isolating Material
A device is disclosed that includes a wafer/chip, a first layer, a first device, an isolation mold and a second device. The first layer is formed over the chip...
2016/0118352 SEMICONDUCTOR DEVICE
To improve reliability of a semiconductor device obtained through a dicing step. In a ring region, a first outer ring is provided outside a seal ring, and a...
2016/0118351 Interconnect Crack Arrestor Structure and Methods
A system and method for preventing cracks is provided. An embodiment comprises placing crack stoppers into a connection between a semiconductor die and a...
2016/0118350 INTERCONNECT ARRANGEMENT WITH STRESS-REDUCING STRUCTURE AND METHOD OF FABRICATING THE SAME
A semiconductor device structure and a method of fabricating the same are provided. The semiconductor structure includes a substrate and an interconnection...
2016/0118349 SEMICONDUCTOR PACKAGE
A semiconductor package includes a dielectric layer, a plurality of traces, a plurality of electrical pads, a plurality of studs and at least a semiconductor...
2016/0118348 STRAIN DETECTION STRUCTURES FOR BONDED WAFERS AND CHIPS
Strain detection structures used with bonded wafers and chips and methods of manufacture are disclosed. The method includes forming lower metal wiring...
2016/0118347 Semiconductor Device and Method
A system and method for a semiconductor device are provided. An embodiment comprises a dielectric layer, a hard mask layer over the dielectric layer, and a...
2016/0118346 DEVICE EMBEDDED SUBSTRATE AND MANUFACTURING METHOD THEREOF
A device embedded substrate includes: an insulating layer; a first metal layer and a second metal layer that are formed such that the insulating layer is...
2016/0118345 LOW TEMPATURE TUNGSTEN FILM DEPOSITION FOR SMALL CRITICAL DIMENSION CONTACTS AND INTERCONNECTS
Provided are methods of void-free tungsten fill of high aspect ratio features. According to various embodiments, the methods involve a reduced temperature...
2016/0118344 Oversized Contacts and Vias in Layout Defined by Linearly Constrained Topology
A rectangular-shaped interlevel connection layout structure is defined to electrically connect a first layout structure in a first chip level with a second...
2016/0118343 SEMICONDUCTOR DEVICE
Low-voltage side wirings LWA and LWB extend in X-direction, respectively, while meandering along a main surface of a semiconductor substrate SUB. A ...
2016/0118342 FUSE STRUCTURE AND METHOD OF BLOWING THE SAME
A fuse structure and a method of blowing the same are provided. The fuse structure includes a conductive line on a substrate, first and second vias on the...
2016/0118341 PRECUT METAL LINES
Embodiments of the present invention provide a method for cuts of sacrificial metal lines in a back end of line structure. Sacrificial Mx+1 lines are formed...
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