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Patent # Description
2016/0118340 Low-Resistance Interconnects and Methods of Making Same
Devices and methods for providing low-resistance interconnects in a semiconductor device are provided. Specifically, one or more embodiments of the present...
2016/0118339 Structure Having Isolated Deep Substrate Vias with Decreased Pitch and Increased Aspect Ratio and Related Method
A structure having isolated deep substrate vias with decreased pitch and increased aspect ratio is disclosed. The structure includes a device layer over a...
2016/0118338 SEMICONDUCTOR STRUCTURES AND FABRICATION METHODS THEREOF
A method for forming a semiconductor structure including providing a substrate; forming a dielectric layer covering a surface of the substrate; forming a...
2016/0118337 EMBEDDED PACKAGES, METHODS OF FABRICATING THE SAME, ELECTRONIC SYSTEMS INCLUDING THE SAME, AND MEMORY CARDS...
An embedded package includes a chip having a top surface on which a connection member is disposed, a first insulation layer surrounding a portion of the chip,...
2016/0118336 SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure...
2016/0118335 TWO STEP METALLIZATION FORMATION
An integrated circuit structure includes a first conductive line, a dielectric layer over the first conductive line, a diffusion barrier layer in the...
2016/0118334 Interconnect Structure and Method of Forming The Same
An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a low-k (LK) dielectric layer...
2016/0118333 Semiconductor Device and Method of Fabricating 3D Package with Short Cycle Time and High Yield
A method of making a semiconductor device comprising the steps of providing a first manufacturing line, providing a second manufacturing line, and forming a...
2016/0118332 Semiconductor Device and Method of Fabricating 3D Package With Short Cycle Time and High Yield
A method of making a semiconductor device comprises the steps of providing a first manufacturing line, providing a second manufacturing line, and forming a...
2016/0118331 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a substrate including a cell array region having a first active region and a peripheral circuit region having a second active...
2016/0118330 REPAIRING LINE STRUCTURE AND CIRCUIT REPAIRING METHOD USING SAME
The present invention discloses a repairing line structure for repairing a breakage at a crossing point of electric wires extending along different directions...
2016/0118329 SEMICONDUCTOR DEVICE
A partition in lattice form forms a plurality of housing sections. A plurality of circuit blocks including a semiconductor block and a terminal base block are...
2016/0118328 MOLDING COMPOUND SUPPORTED RDL FOR IC PACKAGE
A cylindrical molding compound supported RDL for IC package is disclosed wherein a central cavity is formed in the center of the molding compound. A plurality...
2016/0118327 PACKAGE SUBSTRATE AND FLIP-CHIP PACKAGE CIRCUIT INCLUDING THE SAME
This disclosure provides a package substrate, a flip-chip package circuit and their fabrication method. The package substrate includes: a first wiring layer...
2016/0118326 METHOD FOR FABRICATING FAN-OUT WAFER LEVEL PACKAGE AND FAN-OUT WAFER LEVEL PACKAGE FABRICATED THEREBY
A method for fabricating a fan-out wafer level package includes disposing a first semiconductor chip on a dummy substrate, forming a mold substrate on the...
2016/0118325 FABRICATION METHOD OF EMBEDDED CHIP SUBSTRATE
An embedded chip substrate includes a first insulation layer, a core layer, a chip, a second insulation layer, a first circuit layer, and a second circuit...
2016/0118324 WAFER LEVEL PACKAGING APPROACH FOR SEMICONDUCTOR DEVICES
A semiconductor device includes a substrate having a front surface and a back surface, a subassembly on the front surface of the substrate including first and...
2016/0118323 PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF
A method for fabricating a package structure is provided, which includes the steps of: forming a first insulating layer on a carrier; forming a dielectric body...
2016/0118322 LAMINATED SUBSTRATE AND METHOD FOR MANUFACTURING LAMINATED SUBSTRATE
A laminated substrate includes: a core portion; a first wiring portion configured to be stacked on the core portion and to include a first exposed surface...
2016/0118321 LEAD FRAME AND MANUFACTURING METHOD OF LEAD FRAME
A lead frame includes a lead frame body processed in a predetermined shape, and including a notched part provided at an end of the lead frame body, the notched...
2016/0118320 ELECTRONIC DEVICE PROVIDED WITH AN ENCAPSULATION STRUCTURE WITH IMPROVED ELECTRIC ACCESSIBILITY AND METHOD OF...
An electronic device comprising: a semiconductor die integrating an electronic component; a leadframe housing the semiconductor die; a protection body, which...
2016/0118319 SEMICONDUCTOR PACKAGE AND METHOD THEREFOR
In one embodiment, an electronic package structure includes a lead having a first width. An electronic chip having a conductive bump on a major surface, the...
2016/0118318 SEMICONDUCTOR PACKAGE WITH THROUGH SILICON VIA INTERCONNECT
The invention provides a semiconductor package with a through silicon via (TSV) interconnect. An exemplary embodiment of the semiconductor package with a TSV...
2016/0118317 MICROPROCESSOR ASSEMBLY ADAPTED FOR FLUID COOLING
A microprocessor assembly adapted for fluid cooling can include a semiconductor die mounted on a substrate. The semiconductor die can include an integrated...
2016/0118316 THERMALLY CONDUCTIVE SHEET
A thermally conductive sheet, comprising a curable resin composition, thermally conductive fibers, and thermally conductive particles, wherein the thermally...
2016/0118315 Heat Sink Coupling Using Flexible Heat Pipes for Multi-Surface Components
An apparatus including a primary device and at least one secondary device coupled in a planar array to a substrate; a first heat exchanger disposed on the...
2016/0118314 POWER MODULE AND METHOD OF PACKAGING THE SAME
Provided are a power module having an integrated power semiconductor and a method of packaging the same. The power module according to an aspect of the present...
2016/0118313 FAN-OUT WAFER LEVEL PACKAGES CONTAINING EMBEDDED GROUND PLANE INTERCONNECT STRUCTURES AND METHODS FOR THE...
Fan-Out Wafer Level Packages (FO-WLPs) and methods for fabricating FO-WLPs containing Embedded Ground Planes (EGPs) and backside EGP interconnect structures...
2016/0118312 MOLDING COMPOUND SUPPORTED RDL FOR IC PACKAGE
One of the embodiments for a package substrate discloses a molding compound having plurality of metal pillar with middle portion embedded therein; a top end of...
2016/0118311 THIN FILM RDL FOR IC PACKAGE
A package substrate comprising a thin film redistribution layer (RDL) with a plurality of metal pillar configured on chip side is disclosed to thin the...
2016/0118310 SEMICONDUCTOR MODULE
A semiconductor module includes a plurality of insulating circuit boards including semiconductor chips, each of the plurality of insulating circuit boards...
2016/0118309 Minimal Contact Wet Processing Systems and Methods
Embodiments provided herein describe systems and methods for processing substrates. A substrate having a first region and a second region is provided. A...
2016/0118308 Method And Apparatus For Semiconductor Testing At Low Temperature
A method for testing a plurality of semiconductor devices arranged on a strip may include forming an array of semiconductor devices on a frame, wherein contact...
2016/0118307 METHODS AND DEVICES FOR ENHANCING MOBILITY OF CHARGE CARRIERS
Methods and devices for enhancing mobility of charge carriers. An integrated circuit may include semiconductor devices of two types. The first type of device...
2016/0118306 SEMICONDUCTOR DEVICE WITH BURIED METAL LAYER
A semiconductor device includes: a first active region defined by a recess contained in a device isolation film of a semiconductor substrate belonging to a...
2016/0118305 PROCESS FOR INTEGRATED CIRCUIT FABRICATION INCLUDING A LINER SILICIDE WITH LOW CONTACT RESISTANCE
An integrated circuit includes a substrate supporting a transistor having a source region and a drain region. A high dopant concentration delta-doped layer is...
2016/0118304 FABRICATION OF NANOWIRE STRUCTURES
Methods are presented for facilitating fabrication of nanowire structures, such as one or more nanowire field effect transistors. The methods include, for...
2016/0118303 Method of Forming Source/Drain Contact
A method of fabricating a semiconductor device is disclosed. The method includes forming a gate structure over a substrate. The gate structure includes a first...
2016/0118302 GATE STRUCTURE INTEGRATION SCHEME FOR FIN FIELD EFFECT TRANSISTORS
In one embodiment, a semiconductor device is provided that includes a gate structure present on a channel portion of a fin structure. The gate structure...
2016/0118301 PACKAGE WITH METAL-INSULATOR-METAL CAPACITOR AND METHOD OF MANUFACTURING THE SAME
A package includes a chip that has a metal-insulator-metal (MIM) capacitor formed in a first polymer layer and a metallic pillar formed on the MIM capacitor. A...
2016/0118300 WAFER DIE SEPARATION
A method of singulating a wafer starts with fracturing the wafer. The method may also include attaching the dicing tape sheet to a ring frame; relatively...
2016/0118299 METHOD OF FABRICATING SEMICONDUCTOR DEVICE
The method includes disposing semiconductor chips on a package substrate having sawing lines, forming an encapsulant to cover the semiconductor chips on the...
2016/0118298 OXIDE MEDIATED EPITAXIAL NICKEL DISILICIDE ALLOY CONTACT FORMATION
Contact openings are formed into a dielectric material exposing a surface portion of a semiconductor substrate. An interfacial oxide layer is then formed in...
2016/0118297 Metal Pads with Openings in Integrated Circuits
A device includes a metal pad, and a passivation layer including portions overlapping edge portions of the metal pad. A Post-Passivation-Interconnect (PPI)...
2016/0118296 Interlevel Conductor Pre-Fill Utilizing Selective Barrier Deposition
A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a...
2016/0118295 Method for Forming Contact Vias
A method for forming contact vias includes providing a substrate comprising a plurality of contact structures embedded in a first dielectric layer, the...
2016/0118294 METHOD OF PRODUCING BONDED WAFER
Method of producing bonded wafer including thin film on base wafer, including: implanting at least one gas ion selected from hydrogen ion and rare gas ion into...
2016/0118293 METHOD FOR PHOTOLITHOGRAPHY-FREE SELF-ALIGNED REVERSE ACTIVE ETCH
A layer of partially planarized organosilicate (DUO) is spin-coated onto a layer of high density plasma (HDP) oxide on a silicon wafer after the shallow trench...
2016/0118292 INTEGRATED CIRCUITS WITH AN AIR GAP AND METHODS OF PRODUCING THE SAME
Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming an interconnect trench in a...
2016/0118291 MULTI-WAFER ROTATING DISC REACTOR WITH INERTIAL PLANETARY DRIVE
Wafer carriers and methods for moving wafers in a reactor. The wafer carrier may include a platen with a plurality of compartments and a plurality of wafer...
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