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Patent # Description
2016/0118140 SEMICONDUCTOR DEVICE
A semiconductor device includes a word line coupled to a mask ROM memory cell, a bit line pair coupled to the memory cell, a differential sense amplifier for...
2016/0118139 SEMICONDUCTOR DEVICES
A semiconductor device may include a fuse controller and a fuse array. The fuse controller may be configured to generate internal address signals according to...
2016/0118138 PROGRAMMING AN ELECTRICAL FUSE WITH A SILICON-CONTROLLED RECTIFIER
Circuits for programming an electrical fuse, methods for programming an electrical fuse, and methods for designing a silicon-controlled rectifier for use in...
2016/0118137 REDUCTION OF POWER CONSUMPTION IN FLASH MEMORY
Technologies are generally described for systems, devices and methods effective to reduce power consumption in flash memory. In some examples, a bit error rate...
2016/0118136 ERROR DETECTION METHOD
Methods for detecting and correcting defects in a memory array during a memory operation are described. The memory operation may comprise a programming...
2016/0118135 TWO-STROBE SENSING FOR NONVOLATILE STORAGE
A non-volatile storage system includes a plurality of non-volatile storage elements, a plurality of bit lines connected to the non-volatile storage elements, a...
2016/0118134 WORD LINE DEPENDENT TWO STROBE SENSING MODE FOR NONVOLATILE STORAGE ELEMENTS
A non-volatile storage system includes a plurality of non-volatile storage elements, a plurality of bit lines connected to the non-volatile storage elements, a...
2016/0118133 NONVOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME
A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection...
2016/0118132 Low Impact Read Disturb Handling
A storage device system receives read commands from a host device and maintains a read disturb count for distinct zones of each of a plurality of non-volatile...
2016/0118131 Adaptive Program Pulse Duration Based On Temperature
Techniques are provided for reducing program disturb in a memory device. The techniques include compensating for a temperature in the memory device to reduce...
2016/0118130 PERFORMANCE ACCELERATION DURING SHUTDOWN OF A DATA STORAGE DEVICE
A storage device may include a non-volatile memory; and a controller. The controller may be configured to: operate the data storage device in a standard mode...
2016/0118129 READ VOLTAGE ADJUSTMENT
The present disclosure includes apparatuses and methods related to adjusting read voltages of charge-trapping flash memory. An example embodiment apparatus can...
2016/0118128 METHODS FOR REDUCING BODY EFFECT AND INCREASING JUNCTION BREAKDOWN VOLTAGE
Methods for reducing an increase in the threshold voltage of a transistor due to the body effect and increasing the junction breakdown voltage for junctions of...
2016/0118127 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE
For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an...
2016/0118126 NONVOLATILE MEMORY DEVICES AND PROGRAM METHOD THEREOF
A program method of a nonvolatile memory device is provided which includes programming memory cells to a target state using a verification voltage and an...
2016/0118125 COMPACTION PROCESS FOR A DATA STORAGE DEVICE
A data storage device may include a memory die. The memory die may include a memory. A method may include selecting a source compaction block of the memory for...
2016/0118124 Direct-Transfer Marching Memory And A Computer System Using The Same
A direct-transfer marching memory includes an array of memory units, each of the memory units having a sequence of bit-level cells so as to store information...
2016/0118123 NONVOLATILE MEMORY DEVICE, STORAGE DEVICE HAVING THE SAME, OPERATING METHOD THEREOF
An operating method of a nonvolatile memory device includes determining whether a memory block is a selected block, and when the memory block is not the...
2016/0118122 VERTICAL STRUCTURE SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME
A semiconductor memory device includes: a semiconductor region extending vertically from a first region of a substrate; a plurality of gate electrodes disposed...
2016/0118121 Configurable Volatile Memory Data Save Triggers
A volatile memory data save subsystem may include a coupling to a shared power source such as a chassis or rack battery, or generator. A data save trigger...
2016/0118120 RESISTIVE MEMORY SYSTEM, DRIVER CIRCUIT THEREOF AND METHOD FOR SETTING RESISTANCE THEREOF
A resistive memory system, a driver circuit thereof and a method for setting resistances thereof are provided. The resistive memory system includes a memory...
2016/0118119 Memory Programming Methods and Memory Systems
Memory programming methods and memory systems are described. One example memory programming method includes first applying a first signal to a memory cell to...
2016/0118118 Memory Cells, Methods of Forming Memory Cells, and Methods of Programming Memory Cells
Some embodiments include methods in which a memory cell is formed to have programmable material between first and second access lines, with the programmable...
2016/0118117 RESISTIVE MEMORY DEVICE, RESISTIVE MEMORY SYSTEM, AND METHOD OF OPERATING RESISTIVE MEMORY DEVICE
A method of operating a resistive memory device having a plurality of word lines and a plurality of bit lines includes selecting one or more first memory cells...
2016/0118116 FAST READ SPEED MEMORY DEVICE
A memory cell includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a...
2016/0118115 MULTI-LEVEL MEMORY APPARATUS AND DATA SENSING METHOD THEREOF
A multi-level memory device may include a most significant bit (MSB) determination circuit configured to determine a plurality of MSBs by comparing a cell...
2016/0118114 RESISTIVE MEMORY DEVICE, RESISTIVE MEMORY SYSTEM AND METHOD OF OPERATING THE RESISTIVE MEMORY DEVICE
A method of operating a resistive memory device and a resistive memory system including a resistive memory device is for a resistive memory device including a...
2016/0118113 MONOLITHIC THREE DIMENSIONAL MEMORY ARRAYS WITH STAGGERED VERTICAL BIT LINES AND DUAL-GATE BIT LINE SELECT...
A monolithic three-dimensional memory array is provided that includes global bit lines disposed above a substrate, each global bit line having a long axis,...
2016/0118112 NONVOLATILE STORAGE REFLOW DETECTION
A non-volatile storage system includes non-volatile storage elements and one or more managing circuits in communication with the non-volatile storage elements....
2016/0118111 REDUCED LEVEL CELL MODE FOR NON-VOLATILE MEMORY
Apparatuses, systems, methods, and computer program products are disclosed for reduced level cell solid-state storage. A method includes determining that an...
2016/0118110 Simultaneous Multi-Page Commands for Non-Volatile Memories
Mechanisms are provided, in a non-volatile memory device comprising a non-volatile memory and a memory controller, for controlling an operation of the...
2016/0118109 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes a cell string including dummy memory cells and a plurality of memory cells in which n bit data is stored, and a...
2016/0118108 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device having a memory cell array in which a plurality of memory cells are arranged in columns and rows to form a matrix pattern...
2016/0118107 METHODS OF OPERATING SENSE AMPLIFIER CIRCUITS
A method of maintaining a voltage level of a bit line of a sense amplifier circuit includes providing a power supply voltage at a power supply node, receiving...
2016/0118106 SEMICONDUCTOR DEVICE
It is an object of the present invention to provide a device which can be easily manufactured and obtain a ground state of an arbitrary Ising model. A...
2016/0118105 SEMICONDUCTOR DEVICE
Embodiments of the present invention relate to a latch circuit (L20) which latches a data mask signal (DM) in response to a one-shot signal (NS), and changes...
2016/0118104 VOLATILE MEMORY SELF-DEFRESH
Embodiments of the inventive concept include a volatile memory device including a memory cell array, the memory cell array including multiple rows and/or banks...
2016/0118103 SEMICONDUCTOR DEVICE
The problem was that the high-impedance state of the difference between signals DQS and DQSB cannot be prevented from being brought in. With this invention, a...
2016/0118102 METHOD AND APPARATUS FOR WRITING TO A MAGNETIC TUNNEL JUNCTION (MTJ) BY APPLYING INCREMENTALLY INCREASING...
A method of writing to magnetic tunnel junctions (MTJs) of a magnetic memory array includes storing in-coming data in a cache register, reading the present...
2016/0118101 APPARATUSES AND METHODS FOR SETTING A SIGNAL IN VARIABLE RESISTANCE MEMORY
An example of a method reads a spin torque transfer (STT) memory cell, and writes the STT memory cell using information obtained during the reading of the STT...
2016/0118100 DIFFERENTIAL CURRENT SENSING SCHEME FOR MAGNETIC RANDOM ACCESS MEMORY
A circuit includes first and second reference cells and a current sense amplifier. The first and second reference cells are configured to store opposite logic...
2016/0118099 MAGNONIC HOLOGRAPHIC MEMORY AND METHODS
An electronic device using an array of magnetic wave guides is shown. In one example a memory device is shown that utilizes spin waves and a magnet storage...
2016/0118098 MAGNETIC MEMORY
A magnetic memory according to an embodiment includes at least one MTJ element, the MTJ element including: a magnetic multilayer structure including a first...
2016/0118097 BIPOLAR LOGIC GATES ON MOS-BASED MEMORY CHIPS
A system uses both MOS-based and bipolar-based decoding circuitry in an address decoder for MOS-based memory. The system includes a MOS-based memory, which...
2016/0118096 APPARATUSES, CIRCUITS, AND METHODS FOR BIASING SIGNAL LINES
Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line...
2016/0118095 DIE STACK ADDRESS BUS HAVING A PROGRAMMABLE WIDTH
The dies of a stacked die integrated circuit (IC) employ the address bus to indicate the particular die, or set of dies, targeted by data on a data bus. During...
2016/0118094 SEMICONDUCTOR APPARATUS CAPABLE OF SELF-TUNNING A TIMING MARGIN
A semiconductor apparatus may include a delay-locked loop configured to generate a delay-locked clock signal through a delay locking operation of an internal...
2016/0118093 MULTIPLE RETRY READS IN A READ CHANNEL OF A MEMORY
An apparatus having a circuit and a decoder is disclosed. The circuit is configured to adjust an initial one of a plurality of reference voltages in a read...
2016/0118092 DRIVING APPARATUS AND SELECTION OF A DEAD ZONE OF AN INTERNAL VOLTAGE
A driving apparatus includes a control circuit configured to generate a voltage region control signal enabled for a predetermined time according to a command...
2016/0118091 MEMORY DEVICE AND METHOD OF PERFORMING A WRITE OPERATION IN A MEMORY DEVICE
The present invention provides a technique for performing write operations within a memory device comprising an array of memory cells. Wordline driver...
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