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Patent # Description
2016/0126259 ARRAY SUBSTRATE AND METHOD OF PRODUCING THE SAME, DISPLAY PANEL AND DISPLAY DEVICE
Embodiments of the present invention provide an array substrate and a method of producing the same, a display panel and a display device, solving problems of...
2016/0126258 LOW TEMPERATURE POLY-SILICON ARRAY SUBSTRATE AND FORMING METHOD THEREOF
A low temperature poly-silicon (LTPS) array substrate is disclosed. The array substrate includes a first substrate and a stack structure on the first...
2016/0126257 ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE
An array substrate includes a substrate, a plurality of gate lines and a plurality of data lines intersecting each other and being insulating from each other,...
2016/0126256 THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME
A TFT substrate including a base substrate that includes a plurality of pixel areas; a gate line on the base substrate and extending in a first direction; a...
2016/0126255 DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME
A display substrate includes a gate metal pattern including a gate line on a base substrate and extending in a first direction, and a gate electrode...
2016/0126254 DISPLAY DEVICE
A display device includes a first substrate and an insulating layer over the first substrate. The display device further includes a semiconductor layer over...
2016/0126253 Semiconductor Memory Devices Having Increased Distance Between Gate Electrodes and Epitaxial Patterns and...
A semiconductor memory device is provided including a substrate, a plurality of interlayer insulating layers and gate electrodes alternately stacked on the...
2016/0126252 METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE
According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a...
2016/0126251 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME
According to one embodiment, a semiconductor memory device includes a substrate that includes a first region and a second region; a stacked body that is...
2016/0126250 CHARGE-TRAPPING MEMORY DEVICE
A structure and method for providing improved and reliable charge trapping memory device are disclosed herein. A charge trapping field effect transistor (FET)...
2016/0126249 FINFET VERTICAL FLASH MEMORY
A plurality of fin structures containing, from bottom to top, a non-doped semiconductor portion and a second doped semiconductor portion of a first ...
2016/0126248 BAND GAP TAILORING FOR A TUNNELING DIELECTRIC FOR A THREE-DIMENSIONAL MEMORY STRUCTURE
The band gap structure of a tunneling dielectric can be tailored to facilitate programming and erasing of stored information, while enhancing charge storage...
2016/0126247 NONVOLATILE MEMORY DEVICES HAVING SINGLE-LAYERED GATES
A nonvolatile memory device includes an active region extending in a first direction, a first single-layered gate intersecting the active region and extending...
2016/0126246 INTEGRATED CIRCUIT DEVICES HAVING METAL-INSULATOR-SILICON CONTACT AND METHODS OF FABRICATING THE SAME
Integrated circuit devices and methods of forming the devices are provided. The devices may include an active area, a gate electrode in the active area and a...
2016/0126245 EMBEDDED DRAM IN REPLACEMENT METAL GATE TECHNOLOGY
Methods for forming an eDRAM with replacement metal gate technology and the resulting device are disclosed. Embodiments include forming first and second dummy...
2016/0126244 FORMING IV FINS AND III-V FINS ON INSULATOR
A semiconductor structure including: a set of first fins in a pFET region and a set of second fins in an nFET region, the first fins and the second fins are on...
2016/0126243 Semiconductor Device with Enhancement and Depletion FinFET Cells
A semiconductor device includes enhancement FinFET cells and depletion FinFET cells. The enhancement FinFET cells include first gate structures separating...
2016/0126242 ENHANCEMENT MODE INVERTER WITH VARIABLE THICKNESS DIELECTRIC STACK
An enhancement-mode inverter includes a load transistor and a drive transistor. The load transistor has a bottom gate architecture with a first source, a first...
2016/0126241 ENHANCEMENT-DEPLETION MODE INVERTER WITH TWO TRANSISTOR ARCHITECTURES
An enhancement-depletion-mode inverter includes a load transistor and a drive transistor. The load transistor has a top gate architecture with a first source,...
2016/0126240 METHODS AND APPARATUSES FOR FORMING MULTIPLE RADIO FREQUENCY (RF) COMPONENTS ASSOCIATED WITH DIFFERENT RF BANDS...
A device includes a first radio frequency (RF) component on a die. The first RF component includes a first lightly doped region having a first value of a...
2016/0126239 INTEGRATED CIRCUITS WITH RESISTOR STRUCTURES FORMED FROM MIM CAPACITOR MATERIAL AND METHODS FOR FABRICATING SAME
Integrated circuits having resistor structures formed from a MIM capacitor material and methods for fabricating such integrated circuits are provided. In an...
2016/0126238 POWER SOURCE CIRCUIT, ELECTRONIC CIRCUIT, AND INTEGRATED CIRCUIT
A power source circuit includes: a P-type transistor one of a source and a drain of which is connected to a first power source line and the other of the source...
2016/0126237 SEMICONDUCTOR DEVICE
A semiconductor device including metal-on-semiconductor (MOS) and bipolar junction (BJ) structures formed in a substrate. The MOS structure includes a first...
2016/0126236 METHOD OF FORMING A SEMICONDUCTOR DEVICE AND STRUCTURE THEREFOR
In one embodiment, a semiconductor device may include a first transistor having a first current carrying electrode, a second current carrying electrode, and a...
2016/0126235 SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME
A capacitive component region is formed below a temperature detecting diode or below a protective diode. In addition, the capacitive component region is formed...
2016/0126234 BIPOLAR TRANSISTOR INCLUDING LATERAL SUPPRESSION DIODE
A transistor includes an emitter of a first conductivity type, base of a second conductivity type, collector of the first conductivity type, and cathode of a...
2016/0126233 METHOD AND CIRCUITRY FOR ON-CHIP ELECTRO-STATIC DISCHARGE PROTECTION SCHEME FOR LOW COST GATE DRIVER INTEGRATED...
An apparatus includes an integrated circuit, a plurality of bi-directional pins, and an electro-static discharge (ESD) clamp. The integrated circuit is...
2016/0126232 CIRCUIT LAYOUT, LAYOUT METHOD AND SYSTEM FOR IMPLEMENTING THE METHOD
A circuit layout includes a first device having a first set of fingers, wherein the first set of fingers is separated into a first finger group and a second...
2016/0126231 LEDGE-FREE DISPLAY
This disclosure provides systems, methods and apparatus for a ledge-free display. In one aspect, row driver circuits and column driver circuits may be provided...
2016/0126230 TRIPLE STACK SEMICONDUCTOR PACKAGE
A method for forming a stacked semiconductor package includes providing a bottom leadframe (LF) panel including LFs downset each including at least a plurality...
2016/0126229 SEMICONDUCTOR CHIP AND A SEMICONDUCTOR PACKAGE HAVING A PACKAGE ON PACKAGE (POP) STRUCTURE INCLUDING THE...
A semiconductor chip including a substrate, a first data pad arranged on the substrate, and a first control/address pad arranged on the substrate, wherein the...
2016/0126228 FAN-OUT WAFER LEVEL CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A fan-out wafer level chip package structure and the manufacturing method thereof are provided. The method includes the steps of providing a supporting plate...
2016/0126227 Method for Attaching a Semiconductor Die to a Carrier
A method for fabricating an electronic device includes providing a first semiconductor chip and a second semiconductor chip. The first semiconductor chip has a...
2016/0126226 Integrated Fan-Out Structure and Method
A semiconductor package comprises a top package and a bottom package with fan-out interconnect structures. A plurality of inter-package connectors electrically...
2016/0126225 LIGHT-EMITTING DEVICE
A light-emitting device includes light-emitting units and an electrical connection layer. Each light-emitting unit includes a light-emitting stacking layer, a...
2016/0126224 DISPLAY DEVICE USING SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME
A display device includes a first electrode; a second electrode; and a plurality of semiconductor light emitting devices coupled to a conductive adhesive...
2016/0126223 LIGHT-EMITTING DIODE LIGHTING DEVICE
A light-emitting diode (LED) lighting device includes a substrate, a first bottom electrode, a bottom transparent isolation layer, a first vertical LED, a...
2016/0126222 LIGHT-EMITTING DIODE LIGHTING DEVICE
A light-emitting diode (LED) lighting device includes a substrate, a first bottom electrode, a bottom transparent isolation layer, a first vertical LED, a...
2016/0126221 LIGHT-EMITTING DIODE MODULE
A light-emitting diode module for emitting white light includes a first light emitting diode chip for generating radiation in the blue spectral range having a...
2016/0126220 Electrostatic Discharge Protection Structure and Method
A semiconductor package comprises a top package and a bottom package with a plurality of fan-out interconnect structures. A plurality of inter-package...
2016/0126219 PACKAGE INCLUDING A SEMICONDUCTOR DIE AND A CAPACITIVE COMPONENT
In one general aspect, a method can include forming a redistribution layer on a substrate using a first electroplating process, and forming a conductive pillar...
2016/0126218 BONDING METHOD OF SEMICONDUCTOR CHIP AND BONDING APPARATUS OF SEMICONDUCTOR CHIP
According to one embodiment, there is provided a bonding method of a semiconductor chip. The bonding method includes arranging an activated front surface of a...
2016/0126217 SYSTEMS, METHODS AND DEVICES FOR INTER-SUBSTRATE COUPLING
Inter-substrate coupling and alignment using liquid droplets can include electrical and plasmon modalities. For example, a set of droplets can be placed on a...
2016/0126216 Method of forming an interconnection and arrangement for a direct interconnect chip assembly
Various embodiments provide a method of forming an interconnection between an electric component and an electronic component, wherein the method comprises...
2016/0126215 METHOD FOR ASSEMBLING TWO SUBSTRATES OF DIFFERENT NATURES VIA A DUCTILE INTERMEDIATE LAYER
A method for manufacturing a heterostructure, including: contacting a first substrate having a first coefficient of thermal expansion and a second substrate...
2016/0126214 SEMICONDUCTOR PACKAGE WITH ADHESIVE MATERIAL PRE-PRINTED ON THE LEAD FRAME AND CHIP, AND ITS MANUFACTURING METHOD
This invention discloses a semiconductor package with adhesive material pre-printed on the lead frame and chip, and the manufacturing method. The adhesive...
2016/0126213 THERMO-COMPRESSION BONDING SYSTEM, SUBSYSTEMS, AND METHODS OF USE
Co-planarity adjustment systems and methods, gantries capable of applying high force without imposing moment loads to their bearings, systems and methods for...
2016/0126212 CHIP ASSEMBLAGE, PRESS PACK CELL AND METHOD FOR OPERATING A PRESS PACK CELL
One aspect of the invention relates to a chip assemblage. The latter comprises a number of semiconductor chips, each of which has a semiconductor body having...
2016/0126211 SEMICONDUCTOR ARRANGEMENT, METHOD FOR PRODUCING A SEMICONDUCTOR CHIP
A semiconductor assembly is described. In accordance with one example of the invention, the semiconductor assembly comprises a semiconductor body, a top main...
2016/0126210 Electronic Component, System and Method
In an embodiment, an electronic component includes a power semiconductor device embedded in a dielectric core layer and at least one contact layer protruding...
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