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Patent # Description
2016/0126209 SEMICONDUCTOR DEVICE
A semiconductor device includes: an insulating substrate including an insulating plate and a circuit board on the insulating plate; a semiconductor chip having...
2016/0126208 COATED BONDING WIRE AND METHODS FOR BONDING USING SAME
A semiconductor device includes a bond formed on a bond pad. The bond is formed of a wire that includes a central core of conductive metal, a first coating...
2016/0126207 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device includes: a semiconductor element; a joined member that is joined to the semiconductor element and includes a nickel film; and a joining...
2016/0126206 THICK-SILVER LAYER INTERFACE
A semiconductor device and a method of manufacturing the same include a die and a planar thermal layer, and a thick-silver layer having a thickness of at least...
2016/0126205 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SEMICONDUCTOR DEVICE
A semiconductor device includes first and second semiconductor elements and first and second conductive members. A first electrode on the first semiconductor...
2016/0126204 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device includes: arranging a solder material containing at least tin, between a semiconductor element and a joined...
2016/0126203 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME
A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a...
2016/0126202 BRIDGING ARRANGEMENT, MICROELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING A BRIDGING ARRANGEMENT
A bridging arrangement includes a first and a second surface defining a gap therebetween. At least one surface of the first and second surface has an...
2016/0126201 DUAL LAYER STACK FOR CONTACT FORMATION
A semiconductor structures includes a contact fabricated utilizing a multi material trench-layer. The multi material trench layer is utilized to form a contact...
2016/0126200 SEMICONDUCTOR DEVICE PACKAGE WITH INTEGRATED ANTENNA FOR WIRELESS APPLICATIONS
A semiconductor device package is provided with integrated antenna for wireless applications. The semiconductor device package comprises a substrate including...
2016/0126199 SIGNAL PATHS FOR RADIO-FREQUENCY MODULES
Signal paths for radio-frequency (RF) modules. In some embodiments, an RF module can include a plurality of components configured to facilitate processing of...
2016/0126198 Arrangement for Energy Conditioning
Circuit arrangement embodiments that use relative groupings of energy pathways that include shielding circuit arrangements that can sustain and condition...
2016/0126197 SEMICONDUCTOR DEVICE HAVING A STRESS-COMPENSATED CHIP ELECTRODE
A semiconductor device includes a semiconductor chip having a first main surface and a second main surface. A chip electrode is disposed on the first main...
2016/0126196 PRINTED CIRCUIT MODULE HAVING A SEMICONDUCTOR DEVICE WITH A PROTECTIVE LAYER IN PLACE OF A LOW-RESISTIVITY...
A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed...
2016/0126195 NON-MAGNETIC PACKAGE AND METHOD OF MANUFACTURE
A non-magnetic hermetic package includes walls that surround an open cavity, with a generally planar non-magnetic and metallic seal ring disposed in a...
2016/0126194 MEASUREMENT MARK STRUCTURE AND MANUFACTURING METHOD THEREOF
The present invention provides a measurement mark structure, including a plurality of inner patterns, the inner patterns being arranged along a first...
2016/0126193 METHOD OF FABRICATING A TUNGSTEN PLUG IN A SEMICONDUCTOR DEVICE
In an semiconductor process, a seamless tungsten plug is formed in an inter-layer dielectric by forming the inter-layer dielectric from multiple oxide layers...
2016/0126192 Power Semiconductor Module Having a Direct Copper Bonded Substrate and an Integrated Passive Component, and an...
A power semiconductor module includes a direct copper bonded (DCB) substrate having a ceramic substrate, a first copper metallization bonded to a first main...
2016/0126191 METHOD OF FORMING STACKED TRENCH CONTACTS AND STRUCTURES FORMED THEREBY
Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact...
2016/0126190 METHODS OF FORMING AN IMPROVED VIA TO CONTACT INTERFACE BY SELECTIVE FORMATION OF A CONDUCTIVE CAPPING LAYER
One illustrative method disclosed herein includes, among other things, forming an opening in a layer of insulating material so as to thereby expose at least a...
2016/0126189 Programmable Devices and Methods of Manufacture Thereof
Programmable devices, methods of manufacture thereof, and methods of programming devices are disclosed. In one embodiment, a programmable device includes a...
2016/0126188 SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF
One or more techniques for forming a semiconductor arrangement and resulting structures formed thereby are provided herein. The semiconductor arrangement...
2016/0126187 SEMICONDUCTOR DEVICE
A semiconductor device includes: a semiconductor element having a gate and source electrodes; an insulating substrate which is provided with an insulating...
2016/0126186 BOND PAD STRUCTURE WITH DUAL PASSIVATION LAYERS
A bond pad structure with dual passivation layers is disclosed. The bond pad structure includes: a pad material layer on a first passivation layer; a...
2016/0126185 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
A method of forming a semiconductor structure includes the steps: providing a substrate; forming a dielectric over the substrate; forming an opening recessed...
2016/0126184 DIAGONAL HARDMASKS FOR IMPROVED OVERLAY IN FABRICATING BACK END OF LINE (BEOL) INTERCONNECTS
Self-aligned via and plug patterning using diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects is described. In an...
2016/0126183 ELECTRICALLY CONDUCTIVE INTERCONNECT INCLUDING VIA HAVING INCREASED CONTACT SURFACE AREA
An interconnect structure includes a first dielectric layer and a second dielectric layer each extending along a first axis to define a height and a second...
2016/0126182 DUMMY PATTERNS
A semiconductor layout pattern includes a device layout pattern, a plurality of rectangular first dummy patterns having a first size, a plurality of...
2016/0126181 Methods of Fabricating Integrated Circuitry
A method of fabricating integrated circuitry includes forming a first conductive line. First elemental tungsten is deposited directly against an elevationally...
2016/0126180 VIA STRUCTURE FOR OPTIMIZING SIGNAL POROSITY
An apparatus including a conductive stack structure includes an M.sub.x layer interconnect on an M.sub.x layer and extending in a first direction on a first...
2016/0126179 Buried Etch Stop Layer for Damascene Bit Line Formation
A stack of layers is formed that includes first, second, and third dielectric layers. Contact plugs are then formed extending through the stack. Then a fourth...
2016/0126178 MEMORY CELL HAVING MULTI-LEVEL WORD LINE
A memory cell comprises a first word line in a first layer on a first level. The memory cell also comprises a second word line having a first portion in the...
2016/0126177 Packaged Assembly for High Density Power Applications
A packaged assembly for high density power applications includes a case having shelves on opposing walls, and a double-sided substrate disposed on the shelves...
2016/0126176 PACKAGE SUBSTRATE, PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF
A package substrate is provided, which includes: a body having opposite first and second surfaces, each having adjacent first and second regions defined...
2016/0126175 CIRCUIT SUBSTRATE AND SEMICONDUCTOR PACKAGE STRUCTURE
The invention provides a circuit substrate and a semiconductor package structure. The circuit substrate includes a core substrate having a chip-side surface...
2016/0126174 SUBSTRATES AND METHODS OF MANUFACTURE
An interposer (110) has contact pads at the top and/or bottom surfaces for connection to circuit modules (e.g. ICs 112). The interposer includes a substrate...
2016/0126173 HIGH DENSITY FAN OUT PACKAGE STRUCTURE
A high density fan out package structure may include a contact layer. The contact layer includes a conductive interconnect layer having a first surface facing...
2016/0126172 SEMICONDUCTOR DEVICE PACKAGE AND ELECTRONIC DEVICE INCLUDING THE SAME
A semiconductor device package includes a substrate having a first surface and a second surface that is opposite to the first surface, a plurality of solder...
2016/0126171 CIRCUIT BOARD WITH CONSTRAINED SOLDER INTERCONNECT PADS
Various circuit boards and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a solder...
2016/0126170 SOLID STATE CONTACTOR WITH IMPROVED INTERCONNECT STRUCTURE
A printed circuit board for selectively communicating power from a power source to a use has an input bus for receiving a power supply. A transistor is...
2016/0126169 LEADLESS SEMICONDUCTOR DEVICE AND METHOD OF MAKING THEREOF
Consistent with an example embodiment, there is a leadless packaged semiconductor device having top and bottom opposing major surfaces and sidewalls extending...
2016/0126168 SEMICONDUCTOR DEVICE
A first switching element and a second switching element are thermally connected to each other since the first switching element and the second switching...
2016/0126167 SEMICONDUCTOR MODULE, SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR MODULE, AND METHOD OF MANUFACTURING...
A semiconductor module is configured such that heat radiation substrates are connected to lead frames and semiconductor chips are directly connected to the...
2016/0126166 FLIP-CHIP ON LEADFRAME SEMICONDUCTOR PACKAGING STRUCTURE AND FABRICATION METHOD THEREOF
Flip-chip on leadframe (FCOL) semiconductor packaging structure and fabrication method thereof are provided. A semiconductor chip with copper pillars formed...
2016/0126165 METHOD OF CONNECTING A SUBSTRATE AND CHIP ASSEMBLY
A method of connecting a substrate is provided, wherein the substrate may include a first main surface and a second main surface opposite the first main...
2016/0126164 CAVITY PACKAGE WITH PRE-MOLDED CAVITY LEADFRAME
A cavity package is disclosed comprising a metal leadframe, a metal ring connected to the metal leadframe, a plastic body molded to the metal leadframe forming...
2016/0126163 LEAD FRAME STRIP WITH MOLDING COMPOUND CHANNELS
A lead frame strip has a plurality of unit lead frames. Each of the unit lead frames has a periphery structure connecting adjacent ones of the unit lead...
2016/0126162 PACKAGE WITH MULTIPLE I/O SIDE-SOLDERABLE TERMINALS
Consistent with an example embodiment, there is leadless packaged semiconductor device having top and bottom opposing major surfaces and sidewalls extending...
2016/0126161 SEMICONDUCTOR PACKAGE
A semiconductor package includes a packaging substrate having a first surface and a second surface opposite to the first surface; and a semiconductor die...
2016/0126160 SYSTEM FOR COOLING DUAL SIDES OF POWER SEMICONDUCTOR DEVICE
A system for cooling dual sides of power semiconductor devices includes two (2) cooling water flow passages, each of which being bent in the "" or "S" shape,...
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