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Patent # Description
2016/0126159 INTERPOSER FOR MULTI-CHIP ELECTRONICS PACKAGING
An interposer for vertically separating device die is disclosed. The interposer includes a compliant layer comprising a plurality of thermally conductive plugs...
2016/0126158 INTEGRATED CIRCUIT HEAT DISSIPATION USING NANOSTRUCTURES
An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature...
2016/0126157 DOUBLE-SIDED COOLING POWER MODULE AND METHOD FOR MANUFACTURING THE SAME
A double-sided cooling power module may include a lower-end terminal, at least one pair of power semiconductor chips mounted on the lower-end terminal, at...
2016/0126156 SEMICONDUCTOR DEVICE
A ground working tool comprising a tubular base body with an inner receiving space for receiving a cylindrical core of solid ground material, connector...
2016/0126155 SEMICONDUCTOR DEVICE
Provided is a flip-chip mounted semiconductor device in which a crack is less likely to develop. Flip chip mounting is carried out under the condition that no...
2016/0126154 Power Semiconductor Module and Method for Producing a Power Semiconductor Module
A power semiconductor module includes a module housing and a circuit carrier having a dielectric insulation carrier and an upper metallization layer applied...
2016/0126153 PRINTED CIRCUIT BOARD AND ELECTRONIC EQUIPMENT
A plurality of lands is formed apart from each other on a surface of a package substrate. Another plurality of lands is formed apart from each other on a...
2016/0126152 TEST STRUCTURE FOR DETERMINING OVERLAY ACCURACY IN SEMICONDUCTOR DEVICES USING RESISTANCE MEASUREMENT
Provided is a test pattern structure for determining overlay accuracy in a semiconductor device. The test pattern structure includes one or more resistor...
2016/0126151 METHOD FOR PRODUCING A PLURALITY OF MEASUREMENT REGIONS ON A CHIP, AND CHIP WITH MEASUREMENT REGIONS
A a chip and a method for producing the chip with a plurality of measurement regions which are provided with electrodes for electrically detecting reactions in...
2016/0126150 SYSTEM AND METHOD FOR GENERATING AN ARM SCAN PROFILE
A system and method for performing a wet etching process is disclosed. The system includes multiple processing stations accessible by a transfer device,...
2016/0126149 METHOD FOR PROCESSING A SUBSTRATE AND A METHOD OF PROCESS SCREENING FOR INTEGRATED CIRCUITS
According to various embodiments, a method for processing a substrate may include: forming a dielectric layer over the substrate, the dielectric layer may...
2016/0126148 SYSTEM AND METHOD FOR PERFORMING A WET ETCHING PROCESS
A system and method for performing a wet etching process is disclosed. The system includes multiple processing stations accessible by a transfer device,...
2016/0126147 STRUCTURE AND METHOD OF LATCHUP ROBUSTNESS WITH PLACEMENT OF THROUGH WAFER VIA WITHIN CMOS CIRCUITRY
A method of manufacturing a semiconductor structure includes: forming a trench in a back side of a substrate; depositing a dopant on surfaces of the trench;...
2016/0126146 EFFICIENT MAIN SPACER PULL BACK PROCESS FOR ADVANCED VLSI CMOS TECHNOLOGIES
Forming a poly-Si device including pulling back spacers prior to silicidation and the resulting device are provided. Embodiments include forming two poly-Si...
2016/0126145 LOW THRESHOLD VOLTAGE CMOS DEVICE
A replacement metal gate process in which a high-k dielectric is applied. The high-k dielectric may be doped with lanthanum in an NMOS region or aluminum in a...
2016/0126144 METHODS OF FORMING A METAL-INSULATOR-SEMICONDUCTOR (MIS) STRUCTURE AND A DUAL CONTACT DEVICE
A method includes forming a first metal layer on source/drain regions of an n-type metal-oxide-semiconductor (NMOS) device and on source/drain regions of a...
2016/0126143 METHOD OF FORMING HORIZONTAL GATE ALL AROUND STRUCTURE
This disclosure provides a horizontal structure by using a double STI recess method. The double STI recess method includes: forming a plurality of fins on the...
2016/0126142 Equal Gate Height Control Method for Semiconductor Device with Different Pattern Densites
A method of forming a semiconductor integrated circuit (IC) includes forming a first semiconductor layer over a substrate, the first semiconductor layer having...
2016/0126141 METHODS FOR FORMING FINFETS HAVING A CAPPING LAYER FOR REDUCING PUNCH THROUGH LEAKAGE
A method for forming FinFETs having a capping layer for reducing punch through leakage includes providing an intermediate semiconductor structure having a...
2016/0126140 INTEGRATED CIRCUIT STRUCTURE AND METHOD FOR MANUFACTURING THEREOF
A method of manufacturing an integrated circuit structure includes forming a plurality of gate stacks on a first area and a second area of a substrate. A...
2016/0126139 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a high-k dielectric layer thereon;...
2016/0126138 WAFER PROCESSING METHOD
A wafer is formed with a plurality of division lines on a front surface of a single crystal substrate having an off angle and formed with devices in a...
2016/0126137 COMBINING CUT MASK LITHOGRAPHY AND CONVENTIONAL LITHOGRAPHY TO ACHIEVE SUB-THRESHOLD PATTERN FEATURES
Features are fabricated on a semiconductor chip. The features are smaller than the threshold of the lithography used to create the chip. A method includes...
2016/0126136 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device according to an embodiment includes a low-adhesion film, a pair of substrates, and a metal electrode. The low-adhesion film has lower...
2016/0126135 METHODS OF FORMING AN IMPROVED VIA TO CONTACT INTERFACE BY SELECTIVE FORMATION OF A METAL SILICIDE CAPPING LAYER
One illustrative method disclosed herein includes, among other things, forming an opening in at least one layer of insulating material so as to thereby expose...
2016/0126134 SYSTEMS AND METHODS FOR REMOVING CONTAMINATION FROM SEED LAYER SURFACE
An electrochemical deposition plating tool in accordance with one embodiment of the present disclosure includes one or more electrochemical deposition chambers...
2016/0126133 METAL-ASSISTED CHEMICAL ETCHING OF A SEMICONDUCTIVE SUBSTRATE WITH HIGH ASPECT RATIO, HIGH GEOMETIC UNIFORMITY,...
An embodiment of a method for metal-assisted chemical etching of a semiconductive substrate comprises forming a patterned coating on a top surface of a...
2016/0126132 METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH ISOLATION REGIONS HAVING UNIFORM STEP HEIGHTS
Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor...
2016/0126131 Method for Forming a Transistor Structure Comprising a Fin-Shaped Channel Structure
An example method includes providing a layer stack in a trench defined by adjacent STI structures and recessing the STI structures adjacent to the layer stack...
2016/0126130 Air Gaps Structures for Damascene Metal Patterning
A pattern of parallel lines defines first regions where no conductive material is to be located, a distance between adjacent lines in the first regions being...
2016/0126129 CLAMP ASSEMBLY
A clamp assembly is for clamping an outer peripheral portion of a substrate to a support in a plasma processing chamber. An RF bias power is applied to the...
2016/0126128 WAFER ALIGNER
A semiconductor wafer transport apparatus includes a frame, a transport arm movably mounted to the frame and having at least one end effector movably mounted...
2016/0126127 Adhesive Sheet, Method for Manufacturing Semiconductor Device Using Same, Method for Manufacturing Thermal...
Provided is a thermal type airflow volume meter improving measurement accuracy, a method for manufacturing the same, and an adhesive sheet for use therein, the...
2016/0126126 PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF
A method for fabricating a package structure is provided, including the steps of: disposing on a carrier a semiconductor chip having an active surface facing...
2016/0126125 ELECTROSTATIC CHUCK
An electrostatic chuck includes: a body substrate having a substrate front surface and a substrate rear surface and made of ceramic; an attraction electrode...
2016/0126124 ELECTROSTATIC CHUCK
An electrostatic chuck is disclosed. In one aspect, the electrostatic chuck includes a top plate, wherein first and second regions adjacent to each other are...
2016/0126123 Method For Improving Performance Of A Substrate Carrier
A method of modifying a substrate carrier to improve process performance includes depositing material or fabricating devices on a substrate supported by a...
2016/0126122 SUBSTRATE STORING CONTAINER
The bottom plate has a plate-like shape, is arranged to face an outer face of a lower wall, and has a locking portion. The groove member has: a groove-forming...
2016/0126121 SENSOR SYSTEM FOR SEMICONDUCTOR MANUFACTURING APPARATUS
A chamber monitoring system may include a parallel architecture in which a single sensor control system is coupled to a number of different processing chamber...
2016/0126120 WORK-IN-PROGRESS SUBSTRATE PROCESSING METHODS AND SYSTEMS FOR USE IN THE FABRICATION OF INTEGRATED CIRCUITS
Disclosed herein are methods and systems for semiconductor fabrication. In one embodiment, a method for fabricating semiconductors utilizing a semiconductor...
2016/0126119 LASER ANNEALING APPARATUS
A laser annealing apparatus includes a process chamber with a chamber window to transmit a laser beam, and a chuck in the process chamber, a top surface of the...
2016/0126118 PEDESTAL WITH MULTI-ZONE TEMPERATURE CONTROL AND MULTIPLE PURGE CAPABILITIES
Substrate support assemblies for a semiconductor processing apparatus are described. The assemblies may include a pedestal and a stem coupled with the...
2016/0126117 SAMPLE HOLDER
A sample holder of the present invention includes a base body formed of ceramic substrates laminated to each other and having an upper surface functioning as a...
2016/0126116 SINGULATION APPARATUS AND METHOD
A singulation apparatus includes a carrier having a plurality of singulation sites and a scribe line between each of the plurality of singulation sites and an...
2016/0126115 Methods for Controlling Plasma Constituent Flux and Deposition During Semiconductor Fabrication and Apparatus...
A time-dependent substrate temperature to be applied during a plasma process is determined. The time-dependent substrate temperature at any given time is...
2016/0126114 PLASMA PROCESSING APPARATUS
A plasma processing apparatus includes a processing chamber, a table disposed in the processing chamber, a dielectric window provided at the processing...
2016/0126113 ROLL-TYPE PROCESSING MEMBER, PENCIL-TYPE PROCESSING MEMBER, AND SUBSTRATE PROCESSING APPARATUS INCLUDING ANY...
A roll-type cleaning member for scrubbing and cleaning a target cleaning surface of a substrate includes a plurality of nodules formed on a surface thereof....
2016/0126112 SUBSTRATE LIQUID PROCESSING APPARATUS
Gas-liquid separation of an exhaust gas from a liquid processing unit can be improved. A substrate liquid processing apparatus includes a liquid processing...
2016/0126111 METHODS OF MANUFACTURING A PRINTED CIRCUIT MODULE HAVING A SEMICONDUCTOR DEVICE WITH A PROTECTIVE LAYER IN...
A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed...
2016/0126110 METHOD FOR MANUFACTURING THREE-DIMENSIONAL INTEGRATED CIRCUIT
A method for manufacturing a three-dimensional integrated circuit is disclosed. The method includes: providing a substrate; forming at least one metal layer...
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