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Patent # Description
2016/0132451 SYSTEM ON CHIP HAVING SEMAPHORE FUNCTION AND METHOD FOR IMPLEMENTING SEMAPHORE FUNCTION
A system on chip, semiconductor device, and/or method are provided that include a plurality of masters, an interface, and a semaphore unit. The interface...
2016/0132450 NETWORK CONTROLLER - SIDEBAND INTERFACE PORT CONTROLLER
A network interface controller includes a media access controller connected to receive an in-band packet and further connected to receive a sideband packet....
2016/0132449 NETWORK CONTROLLER - SIDEBAND INTERFACE PORT CONTROLLER
A network interface controller includes a media access controller and a host adapter. The host adapter includes a transmit route connected to receive an...
2016/0132448 HUB MODULE WITH A SINGLE BRIDGE SHARED AMONG MULTIPLE CONNECTION PORTS TO SUPPORT ROLE REVERSAL
An apparatus includes a multiport hub, a single bridge configured to communicatively couple together a plurality of hosts and to emulate a slave device to each...
2016/0132447 AGGREGATING COMPLETION MESSAGES IN A SIDEBAND INTERFACE
In one embodiment, the present invention includes a method for receiving a request in a router from a first endpoint coupled to the router, where the request...
2016/0132446 NETWORK SUBSCRIBER
A network subscriber comprises a plurality of individual functional units, each individual functional unit comprising an application interface. The network...
2016/0132445 PERIPHERAL REGISTER PARAMETER REFRESHING
Systems, methods, circuits and computer-readable mediums for peripheral sequencing using an access sequence are disclosed. In some implementations, a control...
2016/0132444 UNIVERSAL ETHERNET SOLUTION
A monolithic integrated circuit that supports multiple industrial Ethernet protocols, fieldbus protocols, and industrial application processing, providing a...
2016/0132443 TRACKING VIRTUAL MACHINE MEMORY MODIFIED BY A SINGLE ROOT I/O VIRTUALIZATION (SR-IOV) DEVICE
Techniques for tracking, by a host system, virtual machine (VM) memory modified by a physical input/output (I/O) device that supports I/O virtualization are...
2016/0132442 DATA WRITING SYSTEM AND METHOD FOR DMA
A data writing system is provided. A processing unit includes at least one core processor. The dynamic random access memory (DRAM) includes a user buffer...
2016/0132441 HETEROGENEOUS MULTIPROCESSOR PLATFORM TARGETING PROGRAMMABLE INTEGRATED CIRCUITS
An integrated circuit (IC) includes a first region being static and providing an interface between the IC and a host processor. The first region includes a...
2016/0132440 MULTI-CHANNEL I2S TRANSMIT CONTROL SYSTEM AND METHOD
A serial peripheral interface is configurable to operate in a I.sup.2S transmission mode. The interface has a transmission unit connected with external pins...
2016/0132439 EXPANDABLE ASYMMETRIC-CHANNEL MEMORY SYSTEM
An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having...
2016/0132438 PROCESSING DEVICE, PROCESSING METHOD, STORAGE MEDIUM, AND ELECTRONIC MUSICAL INSTRUMENT
A processing device includes: a plurality of processing units that perform processes in accordance with data items read from a memory; a bus that connects the...
2016/0132437 PROCESSOR EXTENSIONS FOR EXECUTION OF SECURE EMBEDDED CONTAINERS
Methods and apparatus relating to processor extensions for execution of secure embedded containers are described. In an embodiment, a scalable solution for...
2016/0132436 SYSTEM SUPPORTING MULTIPLE PARTITIONS WITH DIFFERING TRANSLATION FORMATS
A system configuration is provided with multiple partitions that supports different types of address translation structure formats. The configuration may...
2016/0132435 SPINLOCK RESOURCES PROCESSING
According to an example, in a spinlock processing method, a value of a spinlock cache variable may be read from a cache and the value of the spinlock cache...
2016/0132434 STORE CACHE FOR TRANSACTIONAL MEMORY
A method to merge one or more non-transactional stores and one or more thread-specific transactional stores into one or more cache line templates in a store...
2016/0132433 COMPUTER SYSTEM AND CONTROL METHOD
A computer system according to the present invention is composed of a server 200 having a flash memory drive 204 for cache, a storage system 260 having storage...
2016/0132432 Methods for Caching and Reading Data to be Programmed into a Storage Unit and Apparatuses Using the Same
A method for caching and reading data to be programmed into a storage unit, performed by a processing unit, including at least the following steps. A write...
2016/0132431 STORE CACHE FOR TRANSACTIONAL MEMORY
A method to merge one or more non-transactional stores and one or more thread-specific transactional stores into one or more cache line templates in a store...
2016/0132430 Memory Control Circuit and Processor
A memory control circuit has a request determination circuitry to determine whether a period without read-out request and write request to an i-th (i being an...
2016/0132429 Method and Storage Device for Collecting Garbage Data
A method and a storage device for collecting garbage data, where the method includes separately recording a data volume of first data in each segment of a...
2016/0132428 ASSIGNING HOME MEMORY ADDRESSES TO FUNCTION CALL PARAMETERS
Embodiments are directed to assigning a home memory location for a function call parameter. A method may include determining whether a caller is configured to...
2016/0132427 USER INTERFACE CONFORMANCE
Verifying user interface conformance can include deriving a conformance rule set based on desired user interface characteristics identified through an...
2016/0132426 AUTOMATED GENERATION OF SCRIPTED AND MANUAL TEST CASES
Systems and methods that provide manual test cases and scripted test cases automatically based on metadata included in a software application. In an...
2016/0132425 SYSTEM AND METHOD FOR EFFICIENT CREATION AND RECONCILIATION OF MACRO AND MICRO LEVEL TEST PLANS
A method includes creating a macro plan for a test project, creating a micro plan for the test project, wherein the micro plan and the macro plan are based on...
2016/0132424 SIMULATING SENSORS
Simulating sensors can include hooking an application associated with sensory data and associating the sensory data with an automation instruction. Simulating...
2016/0132423 SYSTEM AND METHOD FOR DETERMINING REQUIREMENTS FOR TESTING SOFTWARE
A computer-implemented method, computer program product, and system is provided for determining requirements for testing software. In an implementation, a...
2016/0132422 SYSTEM AND METHOD FOR DETERMINING REQUIREMENTS FOR TESTING SOFTWARE
A computer-implemented method, computer program product, and system is provided for determining requirements for testing software. In an implementation, a...
2016/0132421 ADAPTATION OF AUTOMATED TEST SCRIPTS
Embodiments provide a computerized method for adapting automating test scripts, said method including: utilizing at least one processor to execute computer...
2016/0132420 BACKUP METHOD, PRE-TESTING METHOD FOR ENVIRONMENT UPDATING AND SYSTEM THEREOF
A pre-testing method adapted for environment updating is illustrated. The pre-testing method comprises following steps: while detecting an environment updating...
2016/0132419 OPTIMIZED GENERATION OF DATA FOR SOFTWARE PROBLEM ANALYSIS
A computer optimizes the prospective generation of data used for analysis of a software problem. The computer generates data in accordance with data generation...
2016/0132418 OPTIMIZED GENERATION OF DATA FOR SOFTWARE PROBLEM ANALYSIS
A computer optimizes the prospective generation of data used for analysis of a software problem. The computer generates data in accordance with data generation...
2016/0132417 VERIFYING A GRAPH-BASED COHERENCY VERIFICATION TOOL
Verification is provided of a functional correctness of a graph-based coherency verification tool for logic designs of arrangements of processors and processor...
2016/0132416 COMMUNICATION MONITORING SYSTEM
A communication monitoring system includes a plurality of detecting portions each provided at a connector at an end of a communication cable or at a relay...
2016/0132415 TESTING INSECURE COMPUTING ENVIRONMENTS USING RANDOM DATA SETS GENERATED FROM CHARACTERIZATIONS OF REAL DATA SETS
The disclosed embodiments provide a system that facilitates testing of an insecure computing environment. During operation, the system obtains a real data set...
2016/0132414 SIMULATION DEVICE AND DISTRIBUTION SIMULATION SYSTEM
A simulation apparatus and a distribution simulation system are disclosed. The simulation apparatus, according to one example, includes a simulation executer...
2016/0132413 RECOVERING STRANDED DATA
A system and method for recovering stranded data from a non-volatile memory is provided. An example of a method includes copying data from a non-volatile...
2016/0132412 PERFORMANCE OPTIMIZATION OF READ FUNCTIONS IN A MEMORY SYSTEM
According to one aspect, a method for performance optimization of read functions in a memory system includes receiving, at the memory system, a read request...
2016/0132411 STORAGE CLUSTER FAILURE DETECTION
Direct monitoring of a plurality of storage nodes in a primary cluster is performed based on connectivity with the storage nodes. Indirect monitoring of a...
2016/0132410 KERNEL STATE AND USER STATE DATA EXCHANGE METHOD FOR DISASTER RECOVERY OF VIRTUAL CONTAINER SYSTEM
The present invention relates to a kernel state and user state data exchange method for disaster recovery of a virtual container system. In one disaster...
2016/0132409 MIRRORING IN THREE-DIMENSIONAL STACKED MEMORY
A method for mirroring in three-dimensional-stacked memory includes receiving a plurality of thermal profiles from a plurality of memory chips. The method also...
2016/0132408 MIRRORING IN THREE-DIMENSIONAL STACKED MEMORY
A method for mirroring in three-dimensional-stacked memory includes receiving a plurality of thermal profiles from a plurality of memory chips. The method also...
2016/0132407 FAILOVER SYSTEM AND METHOD OF DECIDING MASTER-SLAVE RELATIONSHIP THEREFOR
A failover system and a method of deciding master-slave relationship therefor are provided. The failover system includes a first electronic device, a second...
2016/0132406 DATA STORAGE DEVICE AND OPERATING METHOD THEREOF
A data storage device includes memory devices including respective main regions and respective virtual regions, and a processor suitable for forming a super...
2016/0132405 METHOD AND APPARATUS FOR REDUNDANCY IN AN ATM USING HOT SWAP HARDWARE UNDERLYING A VIRTUAL MACHINE
A method and apparatus for providing redundancy in an Automatic Teller Machine (ATM) is provided. Application software may be run on top of a virtual...
2016/0132404 METHOD AND APPARATUS FOR REDUNDANCY IN AN ATM USING HOT SWAP HARDWARE UNDERLYING A VIRTUAL MACHINE
A method and apparatus for providing redundancy in an Automatic Teller Machine (ATM) is provided. Application software may be run on top of a virtual...
2016/0132403 FAULT-TOLERANCE THROUGH SILICON VIA INTERFACE AND CONTROLLING METHOD THEREOF
A fault-tolerance through silicon via (TSV) interface is disposed in a three-dimensional random access memory (3-D RAM) with N memory layers and M data access...
2016/0132402 TEST DEVICE AND METHOD FOR CONTROLLING THE SAME
A test device and a method for controlling the test device are disclosed. After a test is interrupted due to a malfunction of the test device, the test device...
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