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Patent # Description
2016/0141258 MULTIPLE BARRIER LAYER ENCAPSULATION STACK
A process for encapsulating an apparatus to restrict environmental element permeation between the apparatus and an external environment includes applying...
2016/0141257 THROUGH-PACKAGE-VIA (TPV) STRUCTURES ON INORGANIC INTERPOSER AND METHODS FOR FABRICATING SAME
Disclosed herein are, for instance, methods for producing through package vias in a glass interposer. For instance, disclosed herein is a method for producing...
2016/0141256 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE
According to various embodiments, a method for manufacturing a semiconductor device may include providing a semiconductor workpiece including a device region...
2016/0141255 SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF
A semiconductor package is provided, which includes: a circuit structure having a first bottom surface and a first top surface opposite to the first bottom...
2016/0141254 CHIP PACKAGE AND METHOD FOR FORMING THE SAME
An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess...
2016/0141253 DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREOF AS WELL AS DISPLAY DEVICE
The embodiments of the present invention provide a display substrate and a manufacturing method thereof, as well as a display device including the display...
2016/0141252 METHODS OF FORMING ALIGNMENT MARKS AND OVERLAY MARKS ON INTEGRATED CIRCUIT PRODUCTS EMPLOYING FINFET DEVICES...
A device disclosed herein includes a plurality of spaced-apart fin structures formed in a semiconductor substrate so as to define an alignment/overlay mark...
2016/0141251 WAFER WITH DIE MAP
Embodiments of the invention provide a semiconductor wafer with information for detecting a die attach pick error on the semiconductor wafer. The semiconductor...
2016/0141250 BARRIER STRUCTURE
A semiconductor device includes a dielectric material and an interconnect structure. The semiconductor device further includes a barrier layer positioned...
2016/0141249 Semiconductor Devices
Semiconductor devices are provided. A semiconductor device includes a substrate, a first conductive structure on the substrate, and a second conductive...
2016/0141248 Chip card module arrangement, chip card arrangement and method for producing a chip card arrangement
A chip card module arrangement may include a first surface and a second surface, which are opposite from one another, and a chip receptacle for one or more...
2016/0141247 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A method of manufacturing a semiconductor device includes forming an opening in a first substrate and filling the opening with a metal to form a first...
2016/0141246 SEMICONDUCTOR DEVICE
A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first interlayer insulating layer including a...
2016/0141245 RADIO-FREQUENCY INTEGRATED CIRCUITS INCLUDING INDUCTORS AND METHODS OF FABRICATING THE SAME
A radio-frequency integrated circuit (RFIC) includes a substrate, an N-type deep well region disposed in an upper region of the substrate and having a top...
2016/0141244 INTEGRATED DEVICE PACKAGE COMPRISING AN ELECTROMAGNETIC (EM) PASSIVE DEVICE IN AN ENCAPSULATION LAYER, AND AN...
Some novel features pertain to an integrated device package that includes a die, an electromagnetic (EM) passive device, an encapsulation layer covering the...
2016/0141243 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate including a first region and a second...
2016/0141242 METHOD AND APPARATUS FOR A HIGH YIELD CONTACT INTEGRATION SCHEME
A methodology for forming contact areas by a multiple patterning process that provides increased yield and lower risk of contact-to-contact short at points of...
2016/0141241 SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
The reliability of a copper wire is improved without inhibiting the wiring resistance of the copper wire. For example, another metallic element segregates in...
2016/0141240 FIELD-EFFECT TRANSISTOR, METHOD OF MANUFACTURING THE SAME, AND RADIO-FREQUENCY DEVICE
There is provided a field-effect transistor including: a gate electrode; a semiconductor layer having a source region and a drain region with the gate...
2016/0141239 METAL PATTERN STRUCTURE HAVING POSITIONING LAYER
A metal pattern structure having a positioning layer thereon is provided. The positioning layer is located within a predetermined region of the metal pattern...
2016/0141238 Semiconductor Device and Method for Forming a Low Profile Embedded Wafer Level Ball Grid Array Molded Laser...
A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An interconnect structure is formed over a...
2016/0141237 THREE DIMENSIONAL ORGANIC OR GLASS INTERPOSER
A three-dimensional organic structure or glass interposer structure and methods of manufacture are disclosed. The method includes forming lined metal vias in a...
2016/0141236 WIRING BOARD, ELECTRONIC COMPONENT DEVICE, METHOD FOR MANUFACTURING WIRING BOARD, AND METHOD FOR MANUFACTURING...
A wiring board includes a first wiring layer, an insulating layer, and a pad. The insulating layer is formed on the first wiring layer. The pad is formed on...
2016/0141235 PRINTED CIRCUIT BOARD ASSEMBLY WITH IMAGE SENSOR MOUNTED THEREON
A printed circuit board assembly (PCBA) and a method to assemble the PCBA are disclosed. The PCBA includes a printed circuit board (PCB), an image sensing chip...
2016/0141234 INTEGRATED DEVICE PACKAGE COMPRISING SILICON BRIDGE IN PHOTO IMAGEABLE LAYER
An integrated device package includes a base portion, a redistribution portion, a first die and a second die. The base portion includes a photo imageable...
2016/0141233 FIRST-PACKAGED AND LATER-ETCHED NORMAL CHIP THREE DIMENSION SYSTEM-IN-PACKAGE METAL CIRCUIT BOARD STRUCTURE AND...
The present invention relates to a first-packaged and later-etched normal chip three dimension-on-chip metal circuit board structure and a processing method...
2016/0141232 INTEGRATED CIRCUIT PACKAGE
An integrated circuit package comprising a semiconductor die, a lead frame lying in a first plane, at least one conductive pillar structure extending outwardly...
2016/0141231 POWER MODULE AND FABRICATION METHOD FOR THE SAME
A power module includes: an insulating layer; a leadframe disposed on the insulating layer; a semiconductor chip disposed on the leadframe; and a mold resin...
2016/0141230 SEMICONDUCTOR DEVICE AND LEAD FRAME HAVING VERTICAL CONNECTION BARS
A semiconductor device includes a lead frame having a die support area and a plurality of inner and outer row leads surrounding the die support area, and a...
2016/0141229 SEMICONDUCTOR PACKAGE WITH SEMICONDUCTOR DIE DIRECTLY ATTACHED TO LEAD FRAME AND METHOD
In one embodiment, a semiconductor package includes a semiconductor die having conductive pads. A lead frame is directly connected to the conductive pads using...
2016/0141228 DEVICE CONNECTION THROUGH A BURIED OXIDE LAYER IN A SILICON ON INSULATOR WAFER
An approach to forming a semiconductor structure for a semiconductor device with connections through a buried oxide layer in a silicon on insulator wafer. A...
2016/0141227 PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF
A method for fabricating a package structure is provided, which includes: providing a first carrier having a circuit layer thereon; forming a plurality of...
2016/0141226 DEVICE CONNECTION THROUGH A BURIED OXIDE LAYER IN A SILICON ON INSULATOR WAFER
An approach to forming a semiconductor structure for a semiconductor device with connections through a buried oxide layer in a silicon on insulator wafer. A...
2016/0141225 LATENT HEAT STORAGE DEVICES
An apparatus including a composite structure including an expanded graphite matrix infiltrated with a phase change material having dimensions configured for...
2016/0141224 POWER MODULE AND FABRICATION METHOD FOR THE SAME
A power module includes: an insulating layer; a leadframe (metal layer) disposed on the insulating layer; a semiconductor chip disposed on the leadframe; and a...
2016/0141223 Method of Manufacturing Heat Conductive Sheet, Heat Conductive Sheet, and Heat Dissipation Member
Provided is a method of manufacturing a heat conductive sheet that itself is imparted with stickiness and has reduced heat resistance due to improved adhesion...
2016/0141222 ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME
In manufacturing an electronic device in which a semiconductor chip including an element layer formed on a front surface of a substrate and a heat sink to...
2016/0141221 ELECTRONIC DEVICE HAVING HEAT CONDUCTING MEMBER
An electronic device includes a semiconductor module, a wiring substrate, a case member and a heat conducting member. The heat conducting member thermally...
2016/0141220 HETERO-BIPOLAR TRANSISTOR AND METHOD FOR PRODUCING THE SAME
A semiconductor device provided with a substrate made of material except for semiconductors and having thermal conductivity greater than that of the...
2016/0141219 CHIP PACKAGE AND METHOD FOR FORMING THE SAME
A chip package includes a chip, a dam layer, a permanent adhesive layer, a support, a buffer layer, a redistribution layer, a passivation layer, and a...
2016/0141218 CIRCUIT MODULE AND MANUFACTURING METHOD THEREOF
There is provided a circuit module where a sufficient amount of underfill resin may be supplied to corner portions of a semiconductor chip. A circuit module...
2016/0141217 ELECTRONIC PACKAGE AND FABRICATION METHOD THEREOF
A method for fabricating an electronic package, including the steps of: providing a substrate having a plurality of electronic elements and a plurality of...
2016/0141216 PROBE PAD WITH INDENTATION
An integrated electronic circuit has probe indentations filled by a hard covering substance. The integrated circuit device results from a process of...
2016/0141215 Method for Manufacturing Semiconductor Device
The reliability of multipoint contact by a contact pin with an external terminal is improved while achieving an improvement in easiness of manufacture of the...
2016/0141214 METHOD FOR MANUFACTURING SEMICONDUCTOR MODULE AND INTERMEDIATE ASSEMBLY UNIT OF THE SAME
A method for manufacturing a semiconductor module includes the step of soldering two or more semiconductor elements having substrate materials and heights...
2016/0141213 AUTOMATED OPTICAL INSPECTION OF UNIT SPECIFIC PATTERNING
A method of automated optical inspection (AOI) for a plurality of unique semiconductor packages can comprise providing a plurality of semiconductor die formed...
2016/0141212 TECHNIQUES AND CONFIGURATIONS TO REDUCE TRANSISTOR GATE SHORT DEFECTS
Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes...
2016/0141211 SEMICONDUCTOR DEVICE INCLUDING POWER AND LOGIC DEVICES AND RELATED FABRICATION METHODS
Semiconductor device structures and related fabrication methods are provided. An exemplary fabrication method involves forming a layer of gate electrode...
2016/0141210 WAFER DICING USING FEMTOSECOND-BASED LASER AND PLASMA ETCH
Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the...
2016/0141209 DEVICE MANUFACTURING METHOD AND DEVICE
A device manufacturing method according to an embodiment includes forming a film on the second surface side of a substrate having a first surface and the...
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