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Patent # Description
2016/0141058 APPARATUS AND METHOD FOR REMOVAL OF NUCLIDES FROM HIGH LEVEL LIQUID WASTES
A method for treating a liquid waste is provided. The method includes supplying the liquid waste to a plurality of cross flow filters from at least one high...
2016/0141057 Excavation and Weld Repair Methodology for Pressurized Water Reactor Piping and Vessel Nozzles
The invention is an innovative design/repair methodology for PWR piping nozzles and vessel nozzles that are attached to the piping/vessel base material with a...
2016/0141056 Passive Nuclear Reactor Emergency Cooling System Using Compressed Gas Energy and Coolant Storage Outside...
A passive safety system for a nuclear power plant (100) cools a nuclear power plant after shutdown (SCRAM) even when all primary water circulation has been...
2016/0141055 PIT GATE, PIT EQUIPMENT, NUCLEAR POWER FACILITY, AND INSTALLATION METHOD OF PIT GATE
A pit gate 15 that is accommodated in a slot 14 and that seals service water retained in a first pit and a second pit in a watertight manner includes a gate...
2016/0141054 IN-VESSEL AND EX-VESSEL MELT COOLING SYSTEM AND METHOD HAVING THE CORE CATCHER
The present invention relates to the in-vessel and ex-vessel melt cooling system having the core catcher. This system includes a reactor vessel having the core...
2016/0141053 SUPERSONIC MOLECULAR BEAM INJECTING DEVICE
This device includes a molecular beam valve, a cold/hot precipitator and a magnetic shielding cylinder, wherein molecular beam valve is nested in cold/hot...
2016/0141052 ELECTRONIC MEMORY DEVICE AND TEST METHOD OF SUCH A DEVICE
The electronic memory device comprises a non-volatile memory matrix organized in rows and columns, an address decoder with address input lines for selecting a...
2016/0141051 SHIFT REGISTER
A shift register comprises a first switch, a second switch, a third switch, and a fourth switch. The first switch selectively conducts a first clock signal to...
2016/0141050 Processor Having a Programmable Function Unit
A processor comprising an ALU a programmable function unit wherein the functional unit may be programmed to comprise multistage logic.
2016/0141049 ANTI-FUSE TYPE ONE-TIME PROGRAMMABLE MEMORY CELL ARRAY AND METHOD OF OPERATING THE SAME
An anti-fuse type one-time programmable (OTP) memory cell array includes a plurality of unit cells which are respectively located at cross points of a...
2016/0141048 BACKGROUND THRESHOLD VOLTAGE SHIFTING USING BASE AND DELTA THRESHOLD VOLTAGE SHIFT VALUES IN NON-VOLATILE MEMORY
In one embodiment, a computer-implemented method includes determining, by a processor, after the writing of data to a non-volatile memory block, one or more...
2016/0141047 Boundary Word Line Operation in Nonvolatile Memory
One or more word lines in a Multi Level Cell (MLC) block are identified as being at high risk of read disturb errors and data is selectively copied from such...
2016/0141046 Techniques for Reducing Read Disturb in Partially Written Blocks of Non-Volatile Memory
Techniques are presented to reduce the amount of read disturb on partially written blocks of NAND type non-volatile memory, both for when determining the last...
2016/0141045 NONVOLATILE MEMORY DEVICE, ERASE METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME
An erase method of a nonvolatile memory device including a plurality of cell strings on a substrate is provided. Each string includes a plurality of memory...
2016/0141044 CONFIGURATION PARAMETER MANAGEMENT USING A CONFIGURATION TOOL
Apparatuses, systems, and methods are disclosed for managing configuration parameters for non-volatile data storage. An initialization module is configured to...
2016/0141043 SEMICONDUCTOR DEVICE
A semiconductor device is provided. The semiconductor device may include a memory block including memory strings connected to respective bit lines coupled to a...
2016/0141042 CONFIGURATION PARAMETER MANAGEMENT FOR NON-VOLATILE DATA STORAGE
Apparatuses, systems, and methods are disclosed for managing configuration parameters for non-volatile data storage. A control module is configured to manage...
2016/0141041 Partial Erase of Nonvolatile Memory Blocks
Erasing blocks of a nonvolatile memory may include two erase steps. A first erase step brings the memory cells of a block to an intermediate state between...
2016/0141040 METHOD FOR ERASING MEMORY CELLS IN A FLASH MEMORY DEVICE USING A POSITIVE WELL BIAS VOLTAGE AND A NEGATIVE WORD...
A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line...
2016/0141039 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device, which restrains a breakdown of a low-voltage transistor constructing a bit line selecting circuit, is provided. An NAND string...
2016/0141038 SEMICONDUCTOR DEVICE
A semiconductor device includes memory blocks including a plurality of memory cells, wherein the plurality of memory cells are divided into a plurality of...
2016/0141037 SEMICONDUCTOR MEMORY SYSTEM AND METHOD OF OPERATING THE SAME
A method of operating a semiconductor memory system includes: programming LSB data into a memory cell of a selected word line included in a memory block;...
2016/0141036 NONVOLATILE MEMORY AND RELATED REPROGRAMMING METHOD
A method of reprogramming a nonvolatile memory device, comprising setting up bit lines of selected memory cells according to logic values of first and second...
2016/0141035 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME
A semiconductor memory device and a method of operating the same are provided. The device may include a memory cell array including a plurality of memory...
2016/0141034 Transistor Design For Use In Advanced Nanometer Flash Memory Devices
Improved PMOS and NMOS transistor designs for sensing circuitry use in advanced nanometer flash memory devices are disclosed.
2016/0141033 MEMORY SYSTEM AND ASSEMBLING METHOD OF MEMORY SYSTEM
According to one embodiment, each memory chip included in a memory package includes a first storage unit that stores therein first information that is n-bit...
2016/0141032 EEPROM ARCHITECTURE WHEREIN EACH BIT IS FORMED BY TWO SERIALLY CONNECTED CELLS
An integrated circuit memory includes memory cells arranged in an array with rows and columns, each column including a first bit line and a second bit line....
2016/0141031 NON-VOLATILE REGISTER FILE INCLUDING MEMORY CELLS HAVING CONDUCTIVE OXIDE MEMORY ELEMENT
Some embodiments include apparatuses and methods having a memory element included in a non-volatile memory cell, a transistor, an access line coupled to a gate...
2016/0141030 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device has at least one memory cell using a resistance variable element, and a control circuit which controls writing to and reading...
2016/0141029 HEALTH DATA ASSOCIATED WITH A RESISTANCE-BASED MEMORY
A method of fabricating a resistance-based memory includes initiating formation of a conductive path through a storage element of the resistance-based memory....
2016/0141028 REFERENCE VOLTAGE GENERATORS AND SENSING CIRCUITS
Described examples include sensing circuits and reference voltage generators for providing a reference voltage to a sensing circuit. The sensing circuits may...
2016/0141027 RESISTANCE VARIABLE MEMORY APPARATUS, READ CIRCUIT UNIT AND OPERATION METHOD THEREFOR
A resistance variable memory apparatus may include: a memory cell array; and a read circuit unit configured to receive a cell current, generate a digital code...
2016/0141026 MEMORY SYSTEM AND METHOD OF OPERATING THE SAME
A memory system includes a memory device including memory blocks, each of the memory blocks including pages, each of the pages including memory cells that are...
2016/0141025 METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE
In method of programming a nonvolatile memory device including a plurality of multi-level cells that store multi-bit data according to example embodiments, a...
2016/0141024 NOVEL NAND ARRAY ARCHITECTURE FOR MULTIPLE SIMUTANEOUS PROGRAM AND READ
This invention discloses a HiNAND array scheme with multiple-level of bit lines (BLs) including metal3 global bit lines (GBLs), divided metal2 Segment bit...
2016/0141023 MEMORY DEVICE
Disclosed is a memory device. The memory device includes a bit-cell comprising a cross-coupled inverter and pass gate transistor connected to data storage node...
2016/0141022 APPARATUS FOR REDUCING WRITE MINIMUM SUPPLY VOLTAGE FOR MEMORY
Described is an apparatus for self-induced reduction in write minimum supply voltage for a memory element. The apparatus comprises: a memory element having...
2016/0141021 SHARED GLOBAL READ AND WRITE WORD LINES
An apparatus includes an array of bit cells that include a first row of bit cells and a second row of bit cells. The apparatus also includes a first global...
2016/0141020 STATIC RANDOM ACCESS MEMORY FREE FROM WRITE DISTURB AND TESTING METHOD THEREOF
A static random access memory (SRAM) includes a memory cell array, a row decoder, a plurality of word-line drivers and an arbiter. The memory cell array...
2016/0141019 MULTI-PORT MEMORY CELL
A circuit includes a first data line, a second data line, a reference node, and a memory cell. The memory cell includes a data node, a first transistor, a...
2016/0141018 MANAGING SKEW IN DATA SIGNALS WITH MULTIPLE MODES
A method for controlling a memory includes causing a data de-skewer to operate in a writing mode, at the data de-skewer, receiving a first signal, and skewing...
2016/0141017 CONTROLLED DYNAMIC DE-ALIGNMENT OF CLOCKS
A controller includes first and second functional units, first and second clock-signal sources that provide corresponding first and second clock signals that...
2016/0141016 CONTROLLED MULTI-STEP DE-ALIGNMENT OF CLOCKS
An apparatus for data processing includes first and second functional units driven by corresponding first and second clock-signal sources, and a...
2016/0141015 MEMORY DEVICE INCLUDING POWER-UP CONTROL CIRCUIT, AND MEMORY SYSTEM HAVING THE SAME
A memory device may include a power-up control circuit and a first set of boost voltage generators. The power-up control circuit may be configured to...
2016/0141014 SEMICONDUCTOR INTEGRATED CIRCUIT
A semiconductor integrated circuit including first semiconductor chip and second semiconductor chip that are vertically stacked, wherein the first ...
2016/0141013 MANAGING SKEW IN DATA SIGNALS WITH ADJUSTABLE STROBE
An apparatus for controlling memory includes a memory controller, and a data interface that interfaces with and is in data communication with data lines, each...
2016/0141012 MANAGING SKEW IN DATA SIGNALS
An apparatus for controlling memory includes a memory controller, and an interface to data lines connecting it to memory. Each line carries a signal that...
2016/0141011 SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF
Provided is a semiconductor device and an operating method thereof. The operating method of the semiconductor device includes performing an erase operation on...
2016/0141010 SEMICONDUCTOR MEMORY APPARATUS AND SYSTEM INCLUDING THE SAME
A semiconductor memory apparatus includes a DBI calculation block, an inversion latch block, an inverted data selective output block, and a pipe latch block....
2016/0141009 SEMICONDUCTOR APPARATUS AND OPERATING METHOD THEREOF
A semiconductor apparatus including a register input selection block configured to serially receive input data and output the input data in parallel as first...
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