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Patent # Description
2016/0148912 SEMICONDUCTOR LIGHT-EMITTING DEVICE HAVING MATRIX-ARRANGED LIGHT-EMITTING ELEMENTS AND TRANSPARENT PLATES
A semiconductor light-emitting device includes a support body multiple, multiple light-emitting elements arranged in a matrix on the support body, a...
2016/0148911 ULTRA-SMALL LED ELECTRODE ASSEMBLY AND METHOD FOR MANUFACTURING SAME
Provided are a nano-scale LED assembly and a method for manufacturing the same. First, a nano-scale LED device that is independently manufactured may be...
2016/0148910 Semiconductor Device Having Plural Memory Chip
A semiconductor device includes a stacked plurality of memory chips. The memory chips each include a plurality of memory banks, a plurality of read/write buses...
2016/0148909 SEMICONDUCTOR PACKAGES HAVING THROUGH ELECTRODES AND METHODS OF FABRICATING THE SAME
Provided are semiconductor packages having through electrodes and methods of fabricating the same. The method may include may include forming a wafer-level...
2016/0148908 MULTI-CHIP PACKAGE SYSTEM
A multi-chip package system includes a signal transmission line commonly coupled to a plurality of semiconductor chips to transfer data to/from the...
2016/0148907 SEMICONDUCTOR DEVICE
One semiconductor device includes nine surface micro-bumps laid out in a 3.times.3 matrix on a semiconductor substrate, a transistor that contains first and...
2016/0148906 SEMICONDUCTOR PACKAGES AND FABRICATION METHOD THEREOF
A semiconductor package and a method of fabricating the same are provided. The semiconductor package may include a first semiconductor chip with a first...
2016/0148905 SEMICONDUCTOR CHIP FOR SENSING TEMPERATURE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME
In one example embodiment, a semiconductor system includes a first chip configured to generate first temperature information of the first chip, the first...
2016/0148904 3D INTEGRATION OF FANOUT WAFER LEVEL PACKAGES
Fanout wafer level packages (FOWLPs) and methods of formation are described. In an embodiment, a package includes a first routing layer, a first die on a top...
2016/0148903 Integrated Circuit Packages and Methods of Forming Same
Packages and methods of manufacture thereof are described. A package may include a first package and a die structure disposed over the first package. The first...
2016/0148902 THERMALLY-ENHANCED THREE DIMENSIONAL SYSTEM-IN-PACKAGES AND METHODS FOR THE FABRICATION THEREOF
Embodiments of three dimensional (3D) System-in-Package (SiPs) and methods for producing 3D SiPs having improved heat dissipation capabilities are provided. In...
2016/0148901 INTERCONNECT CIRCUITS AT THREE-DIMENSIONAL (3-D) BONDING INTERFACES OF A PROCESSOR ARRAY
Embodiments of the invention relate to processor arrays, and in particular, a processor array with interconnect circuits for bonding semiconductor dies. One...
2016/0148900 METHOD FOR BONDING WITH A SILVER PASTE
Disclosed is a method for bonding with a silver paste, the method including: coating a silver paste on a semiconductor device or a substrate, the silver paste...
2016/0148899 METHOD OF DETERMINING CURING CONDITIONS, METHOD OF PRODUCING CIRCUIT DEVICE, AND CIRCUIT DEVICE
A method of determining curing conditions is for determining the curing conditions of a thermosetting resin to seal a conductive part between a substrate and...
2016/0148898 WIRE SPOOL SYSTEM FOR A WIRE BONDING APPARATUS
Disclosed is a wire spool system for a wire bonding apparatus, comprising: a wire reel arranged to receive a wire; a wire guide for feeding a free end of the...
2016/0148897 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a corner constituted by a first side and a second side being perpendicular to the first side; and a plurality of pads including...
2016/0148896 SEMICONDUCTOR DEVICE WITH A WIRE BONDING AND A SINTERED REGION, AND MANUFACTURING PROCESS THEREOF
An electronic device includes: a semiconductor body; a front metallization region; a top buffer region, arranged between the front metallization region and the...
2016/0148895 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A method for manufacturing a semiconductor device, includes providing a wiring substrate having a first surface and a second surface, the first surface being...
2016/0148894 CONDUCTIVE DIE ATTACH FILM FOR LARGE DIE SEMICONDUCTOR PACKAGES AND COMPOSITIONS USEFUL FOR THE PREPARATION THEREOF
Provided herein are conductive die attach films having advantageous properties for use in a variety of applications, e.g., for the preparation of large die...
2016/0148893 WAFER LEVEL PACKAGING USING A CATALYTIC ADHESIVE
Wafer level packaging includes a first layer of a catalytic adhesive on a wafer surface. The catalytic adhesive includes catalytic particles that will reduce...
2016/0148892 SOLDER IN CAVITY INTERCONNECTION STRUCTURES
The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first...
2016/0148891 SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a semiconductor chip; a substrate facing an...
2016/0148890 Method and Apparatus for Cooling Semiconductor Device Hot Blocks and Large Scale Integrated Circuit (IC) Using...
A method, system, and apparatus for improved IC device packaging is described. In an aspect, an (IC) device package includes an IC die having at one or more...
2016/0148889 System and Method for an Improved Fine Pitch Joint
Presented herein are an interconnect and method for forming the same, the method comprising forming an interconnect on a mounting surface of a mounting pad...
2016/0148888 SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME
A semiconductor device may include a semiconductor substrate, a conductive pad on the semiconductor substrate, a passivation layer overlying the semiconductor...
2016/0148887 Device Package with Reduced Thickness and Method for Forming Same
A device package includes a die and a molding compound around the die. The molding compound has a non-planar surface recessed from a top surface of the die....
2016/0148886 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a substrate layer, a redistribution layer (RDL) disposed over the substrate layer, a conductive bump disposed over the RDL, and...
2016/0148885 Cu Core Ball
A Cu core ball is provided that prevents any soft errors and decreases any connection failure. The Cu core ball includes a solder plating film formed on the...
2016/0148884 MEMORY APPARATUS HAVING POWER PAD
A memory apparatus includes a pad, an internal circuit that is connected with the pad, a power connection unit connected with power meshes, and a first...
2016/0148883 Bond Pad Having Ruthenium Covering Passivation Sidewall
A method of forming bond pads includes providing a substrate including an integrated circuit (IC) device formed thereon having an oxidizable uppermost metal...
2016/0148882 Semiconductor Device and Method of Forming Holes in Substrate to Interconnect Top Shield and Ground Shield
A semiconductor device includes a multi-layer substrate. A ground shield is disposed between layers of the substrate and electrically connected to a ground...
2016/0148881 Semiconductor Packages
Semiconductor packages are provided. The semiconductor packages may include a base film having a top surface and a bottom surface, a circuit pattern disposed...
2016/0148880 ELECTRONIC DEVICE WITH STACKED CHIPS
An electronic device includes a first and a second integrated-circuit chip that are stacked at a distance from one another, and a plurality of electrical...
2016/0148879 METHOD FOR FABRICATING AN ELECTRONIC DEVICE AND A STACKED ELECTRONIC DEVICE
A method for fabricating an electronic device, and an electronic device in a stacked configuration, includes a rear face of an integrated-circuit chip that is...
2016/0148878 SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR PATTERN STRUCTURE
A semiconductor pattern structure includes a substrate, an input/output (I/O) region defined on the substrate, a core region defined on the substrate, a dummy...
2016/0148877 QFN PACKAGE WITH IMPROVED CONTACT PINS
According to an embodiment of the present disclosure, a method for manufacturing an integrated circuit (IC) device may include mounting an IC chip onto a...
2016/0148876 FLAT NO-LEADS PACKAGE WITH IMPROVED CONTACT PINS
According to an embodiment of the present disclosure, a leadframe for an integrated circuit (IC) device may comprise a center support structure for mounting an...
2016/0148875 SEMICONDUCTOR ELEMENT SUBSTRATE, AND METHOD FOR PRODUCING SAME
A diffusion time when forming an isolation region is shortened without deteriorating strength against wafer cracks. A plurality of circular holes 4a and 4b are...
2016/0148874 Method for Forming Interconnect Structure that Avoids via Recess
A method for forming an interconnect structure includes forming a dielectric material layer on a semiconductor substrate. The dielectric material layer is...
2016/0148873 ELECTRONIC PACKAGE AND FABRICATION METHOD THEREOF
A method for fabricating an electronic package is provided, which includes the steps of: providing a substrate having a cavity and a first via hole; disposing...
2016/0148872 SEMICONDUCTOR DEVICE HAVING REDUCED CONTACT RESISTANCE
A semiconductor device including at least one self-aligned contact has at least one gate electrode on a bulk substrate layer of the semiconductor device. A...
2016/0148871 ELECTRONIC COMPONENT AND METHOD FOR PRODUCING THE SAME
An aspect of the invention is an electronic component including a semiconductor substrate 11 that has an electrode pad 12, a first resin layer 14 and a third...
2016/0148870 LOW-K DIELECTRIC PORE SEALANT AND METAL-DIFFUSION BARRIER FORMED BY DOPING AND METHOD FOR FORMING THE SAME
A diffusion barrier and a method to form the diffusion bather are disclosed. A trench structure is formed in an Inter Layer Dielectric (ILD). The ILD comprises...
2016/0148869 METHOD AND STRUCTURE TO CONTACT TIGHT PITCH CONDUCTIVE LAYERS WITH GUIDED VIAS
An apparatus including a circuit substrate; a first interconnect layer in a first plane on the substrate and a second interconnect layer in a different second...
2016/0148868 PRECISION INTRALEVEL METAL CAPACITOR FABRICATION
A method for fabricating, within an integrated circuit (IC), a capacitor that includes a first plate formed within a recess of a metal layer that includes a...
2016/0148867 NANOSCALE INTERCONNECT STRUCTURE
An interconnect structure includes a first dielectric material having an undercut region located at an upper surface thereof. A first conductive structure is...
2016/0148866 ELECTRICAL INTERCONNECT FOR AN ELECTRONIC PACKAGE
Some example forms relate to an electrical interconnect for an electronic package. The electrical interconnect includes a dielectric layer that includes a...
2016/0148865 Electronic Circuit Board, Semiconductor Device Using the Same and Manufacturing Method for the Same
The present invention aims to provide an electronic circuit board with insulation reliability improved by increasing volume resistivity of a ceramics substrate...
2016/0148864 INTEGRATED DEVICE PACKAGE COMPRISING HETEROGENEOUS SOLDER JOINT STRUCTURE
Some features pertain to an integrated circuit device that includes a first package substrate, a first die coupled to the first package substrate, a second...
2016/0148863 NON-CONTIGUOUS DUMMY STRUCTURE SURROUNDING THROUGH-SUBSTRATE VIA NEAR INTEGRATED CIRCUIT WIRES
A three-dimensional (3-D) integrated circuit wiring including a plurality of stacked dielectric levels formed on a substrate includes a plurality of...
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