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Patent # Description
2016/0148712 PRODUCTIONS OF RADIOISOTOPES
The present disclosure generally relates to methods and structures for the production of radioisotopes from the thermal neutron irradiation of selected natural...
2016/0148711 NUCLEAR FACILITY POOL CLEANING DEVICE
The invention relates to a nuclear facility pool cleaning device having a floating platform, capable of floating in water, having buoyancy bodies; a drive...
2016/0148710 NUCLEAR FISSION IGNITER
Illustrative embodiments provide nuclear fission igniters for nuclear fission reactors and methods for their operation. Illustrative embodiments and aspects...
2016/0148709 STABLE STARTUP SYSTEM FOR NUCLEAR REACTOR
A stable startup system includes a reactor vessel containing coolant, a reactor core submerged in the coolant, and a heat exchanger configured to remove heat...
2016/0148708 Defect Logging in Nonvolatile Memory
A method of operating a nonvolatile memory block includes reading data from physical units in the block and determining individual error rates for data from...
2016/0148707 Computer System Predicting Memory Failure
The prediction of memory failure is obtained by reducing the voltage on a bank of memory cells to momentarily artificially age the memory cells and subjecting...
2016/0148706 COMPACT SAMPLE-AND-HOLD DEVICE
The sample-and-hold device comprises a holding capacitor and operates according to a track phase during which the voltage on the terminals of the capacitor...
2016/0148705 ONE-TIME PROGRAMMABLE (OTP) MEMORY CELL AND OTP MEMORY DEVICE FOR MULTI-BIT PROGRAM
A one-time programmable (OTP) memory device includes a memory cell array including a plurality of OTP memory cells, the plurality of OTP memory cells being...
2016/0148704 ELECTRONIC DEVICE AND OPERATING METHOD THEREOF
An embodiment of an electronic device is provided. The electronic device includes a read only memory (ROM) and a chip. The ROM includes a plurality of blocks....
2016/0148703 OPERATION METHOD OF NONVOLATILE MEMORY SYSTEM
An operation method of a nonvolatile memory system in accordance with example embodiments of inventive concepts includes detecting an on-cell count of the...
2016/0148702 CALIBRATING OPTIMAL READ LEVELS
After a predetermined period of time in a life cycle of a flash memory device, a plurality of reliability values corresponding to a plurality of reads of one...
2016/0148701 READ LEVEL GROUPING ALGORITHMS FOR INCREASED FLASH PERFORMANCE
A plurality of flash memory wordlines of a flash storage device are divided into a plurality of wordline groups based on read error counts associated with the...
2016/0148700 MEMORY SYSTEM AND DATA PROCESING METHOD FOR MEMORY
The present invention relates to a memory system and a data processing method in a memory, and more particularly, to a memory system for efficiently processing...
2016/0148699 AUTOMATIC PROGRAM OF NON-VOLATILE MEMORY AND AUTOMATIC CYCLING METHOD THEREOF
Disclosed is a memory test method including receiving a memory test command, receiving pattern information for generating a data pattern to be written in a...
2016/0148698 NONVOLATILE MEMORY AND ERASING METHOD THEREOF
An erase method of a nonvolatile memory includes supplying an erase voltage to a substrate, supplying a selection word line voltage to word lines connected...
2016/0148697 Compact Non-Volatile Memory Device
A non-volatile memory device includes a matrix memory plane with columns of memory words respectively formed on each row of the memory plane by groups of...
2016/0148696 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME
A semiconductor memory device and a method of operating the same are provided. The semiconductor memory device includes a plurality of memory layers stacked on...
2016/0148695 DATA STORAGE DEVICE AND METHOD OF PROGRAMMING MEMORY CELLS
A method of programming a non-volatile memory device includes programming memory cells selected from the plurality of memory cells by increasing turn values of...
2016/0148694 VARIANT OPERATION SEQUENCES FOR MULTIBIT MEMORY
A multiple-bit-per-cell, page mode memory comprises a plurality of physical pages, each physical page having N addressable pages p(n). Logic implements a...
2016/0148693 SEMICONDUCTOR DEVICE
A semiconductor device is provided. The semiconductor device may include a memory block including memory cells, the memory cells connected to a word line. The...
2016/0148692 PAGE BUFFER CIRCUIT AND OPERATING METHOD OF SAME
A page buffer circuit includes a plurality of page buffers including a first page buffer. The first page buffer is configured to load input data of the first...
2016/0148691 NAND Boosting Using Dynamic Ramping of Word Line Voltages
Methods for improving channel boosting and reducing program disturb during programming of memory cells within a memory array are described. The memory array...
2016/0148690 SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF
The present invention relates to a semiconductor memory device and an operating method thereof. The semiconductor memory device may include at least two memory...
2016/0148689 Sense Amplifier for Single-ended Sensing
A single ended line sense amplifier having an input coupled to a single ended line having a near end and a far end device comprises a plurality of nFET stacks...
2016/0148688 Sense Amplifier having a Timing Circuit for a Presearch and a Main Search
A line sense amplifier comprises: a presearch block, a main search block, and a timing circuit. The presearch block is coupled to a presearch line for sensing...
2016/0148687 DEVICES AND METHODS FOR WRITING TO A MEMORY CELL OF A MEMORY
A method for writing to a memory is disclosed. The method includes generating a write current that flows to a memory cell of the memory, generating a mirror...
2016/0148686 MEMORY CELL ARRAY OF RESISTIVE RANDOM-ACCESS MEMORIES
A memory cell array includes a first bit line, a first word line, a first source line pair and a first memory cell. A select terminal of the first memory cell...
2016/0148685 RESISTIVE MEMORY WITH PROGRAM VERIFY AND ERASE VERIFY CAPABILITY
A resistive non-volatile memory cell is programmed. A programming voltage is applied to a first terminal of the resistive non-volatile memory cell. Sensing,...
2016/0148684 RESISTIVE RANDOM ACCESS MEMORY AND MANUFACTURING AND CONTROL METHODS THEREOF
A high-reliability resistive random access memory (RRAM). A memory cell of a memory cell array is controlled via a word line, a bit line and a source line. The...
2016/0148683 RESISTIVE MEMORY DEVICE AND METHOD OF OPERATING THE SAME
A memory device includes a memory cell array having multiple memory cells arranged respectively in regions where first signal lines cross second signal lines....
2016/0148682 MEMORY DEVICE REDUCING TEST TIME AND COMPUTING SYSTEM INCLUDING THE SAME
A memory device includes memory cell array and an address decoder. The memory cell array includes a normal memory region and a redundant memory region. The...
2016/0148681 PARALLEL FORMING OF MEMORY CELLS
A method of parallel forming of memory cells, and an apparatus including a memory and a multiplexer. The memory has an array of memory cells and bit lines,...
2016/0148680 TAMPER-RESISTANT NON-VOLATILE MEMORY DEVICE
A non-volatile memory device includes a memory cell array including memory cells, each having a resistance value reversibly transitioning among resistance...
2016/0148679 TAMPER-RESISTANT NON-VOLATILE MEMORY DEVICE
A non-volatile memory device includes a memory cell array including memory cells, a read circuit that, in operation, obtains pieces of resistance value...
2016/0148678 CROSS-POINT MEMORY DEVICE INCLUDING MULTI-LEVEL CELLS AND OPERATING METHOD THEREOF
A method of operating a cross-point memory device, having an array of multilevel cells, includes performing a first reading operation with respect to the...
2016/0148677 METHOD FOR WRITING DATA INTO FLASH MEMORY AND RELATED CONTROL APPARATUS
A method for writing data into a flash memory, wherein the flash memory includes a plurality multi-level cells, and each of the plurality of multi-level cells...
2016/0148676 METHOD OF USING A STATIC RANDOM ACCESS MEMORY
A method of using a static random access memory (SRAM) includes pre-discharging a data line to a reference voltage, activating a bit cell connected to the data...
2016/0148675 SCALABLE FLOATING BODY MEMORY CELL FOR MEMORY COMPILERS AND METHOD OF USING FLOATING BODY MEMORIES WITH MEMORY...
A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays is provided. A method of selecting a floating...
2016/0148674 Systems and Methods for Reducing Standby Power in Floating Body Memory Devices
Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters...
2016/0148673 FIRST DATA IN RESPONSE TO SECOND READ REQUEST
First and second read requests are received. First data is fetched in response to the first read request. The fetched first data is then stored. The fetched...
2016/0148672 SEMICONDUCTOR DEVICE HAVING A REDUCED FOOTPRINT OF WIRES CONNECTING A DLL CIRCUIT WITH AN INPUT/OUTPUT BUFFER
An apparatus includes a clock terminal configured to receive an external clock signal, a clock generator configured to generate an internal clock signal in...
2016/0148671 MEMORY CONTROLLER WITH CLOCK-TO-STROBE SKEW COMPENSATION
A clock signal is transmitted to first and second integrated circuit (IC) components via a clock signal line, the clock signal having a first arrival time at...
2016/0148670 SYSTEMS AND METHODS FOR REDUCING VOLATILE MEMORY STANDBY POWER IN A PORTABLE COMPUTING DEVICE
Various embodiments of systems and methods are disclosed for reducing volatile memory standby power in a portable computing device. One such method involves...
2016/0148669 CONVERSION BOARD AND MOTHERBOARD HAVING SAME
A motherboard includes a first memory, a power supply, a jumper, a second memory slot and a conversion board. A first idle pin of the second memory slot is...
2016/0148668 CELL ARRAY, MEMORY, AND MEMORY SYSTEM INCLUDING THE SAME
A memory includes a first cell array configured to include a plurality of first memory cells connected to a plurality of word lines, a second cell array...
2016/0148667 MAGNETIC RANDOM ACCESS MEMORY WITH DYNAMIC RANDOM ACCESS MEMORY (DRAM)-LIKE INTERFACE
A memory device includes a magnetic memory unit for storing a burst of data during a burst write operation. Each burst of data includes sequential data units...
2016/0148666 MAGNETIC TUNNEL JUNCTION RESISTANCE COMPARISON BASED PHYSICAL UNCLONABLE FUNCTION
A method includes coupling a first magnetic tunnel junction (MTJ) element and a second MTJ element to a comparison circuit. The method also includes comparing,...
2016/0148665 FERROMAGNETIC DEVICE PROVIDING HIGH DOMAIN WALL VELOCITIES
The invention is directed to a method of manufacturing a ferromagnetic device (10), having an elongated structure extending along a longitudinal direction...
2016/0148664 TAMPER-RESISTANT NON-VOLATILE MEMORY DEVICE
A non-volatile memory device includes a memory cell array including memory cells, each having a resistance value reversibly transitioning among resistance...
2016/0148663 RECEIVING CIRCUIT, MEMORY INTERFACE CIRCUIT, AND RECEIVING METHOD
A receiving circuit that receives differential data strobe signals between a controller and a memory, the receiving circuit includes: a first receiver that...
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