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Patent # Description
2016/0147712 DYNAMICAL METHODS FOR SOLVING MIXED-INTEGER OPTIMIZATION PROBLEMS
A dynamical method and system generate a global optimal solution to a mixed integer nonlinear programming (MINLP) problem, where a part or all of optimization...
2016/0147711 DEVICE AND METHOD FOR DETERMINING A ROUGH COMPONENT OF A LATITUDE OR LONGITUDE POSITION OF A MOVING CRAFT
A device and a method for determining a rough component of a latitude or longitude position of a moving craft. The position is reconstructed cyclically by...
2016/0147710 PROVIDING REMOTE, RELIANT AND HIGH PERFORMANCE PCI EXPRESS DEVICE IN CLOUD COMPUTING ENVIRONMENTS
A system architecture, a method, and a computer program product are disclosed for attaching remote physical devices. In one embodiment, the system architecture...
2016/0147709 PROVIDING REMOTE, RELIANT AND HIGH PERFORMANCE PCI EXPRESS DEVICE IN CLOUD COMPUTING ENVIRONMENTS
A system architecture, a method, and a computer program product are disclosed for attaching remote physical devices. In one embodiment, the system architecture...
2016/0147708 BUS SERIALIZATION FOR DEVICES WITHOUT MULTI-DEVICE SUPPORT
A serial bus is provided with a device (sometimes herein referred to as an I2C serializer device) including circuitry and machine logic that operates as...
2016/0147707 BUS SERIALIZATION FOR DEVICES WITHOUT MULTI-DEVICE SUPPORT
A serial bus is provided with a device (sometimes herein referred to as an I2C serializer device) including circuitry and machine logic that operates as...
2016/0147706 SYSTEM AND METHOD FOR IMPROVING THE EFFICIENCY OF A SERIAL INTERFACE PROTOCOL
A link layer of a serial protocol is modified to perform early primitive detection. An early primitive detector unit compares an undecoded bit sequence to that...
2016/0147705 IMPLEMENTING HEALTH CHECK FOR OPTICAL CABLE ATTACHED PCIE ENCLOSURE
A method, system and computer program product are provided for implementing health check for optical cable attached Peripheral Component Interconnect Express...
2016/0147704 Displayport over USB Mechanical Interface
Various exemplary embodiments relate to a function selector device in a system using a DisplayPort protocol over a universal serial bus (USB) mechanical...
2016/0147703 BIDIRECTIONAL COMMUNICATION METHOD AND BIDIRECTIONAL COMMUNICATION APPARATUS USING THE SAME
A communication method according to the present embodiment is a communication method between a first side and a second side operating with a clock provided by...
2016/0147702 COMMUNICATION CONTROL DEVICE, METHOD OF COMMUNICATING A FRAME, AND STORAGE MEDIUM
A communication control device includes a plurality of ports, a memory, and a processor. The memory stores one or more pieces of identification information...
2016/0147701 BRIDGE FOR BUS-POWERED PERIPHERAL DEVICE POWER MANAGEMENT
Technologies are described herein for power management in a peripheral device. A bridge is coupled to a communication link that provides power. The bridge...
2016/0147700 PLACEMENT OF INPUT / OUTPUT ADAPTER CARDS IN A SERVER
Tracking data transfers in an input/output adapter card system to determine whether the adapter cards are well-placed with respect to the components (for...
2016/0147699 METHOD AND SYSTEM FOR A FLEXIBLE INTERCONNECT MEDIA IN A POINT-TO-POINT TOPOGRAPHY
A method and an information handling system provide flexible interconnections between two endpoints and in particular to allow for the allocation and...
2016/0147698 System With Speaker, Transceiver and Related Devices
An audio system includes a docking cradle for receiving and supporting a portable device. The docking cradle includes an interface for providing a connection...
2016/0147697 DETECTING AND CONFIGURING OF EXTERNAL IO ENCLOSURE
A method, system and computer program product are provided for detecting and configuring an external input/output (IO) enclosure in a computer system. A PCIE...
2016/0147696 CONFIGURING A COMMUNICATION INTERCONNECT FOR ELECTRONIC DEVICES
Logic determines a connection arrangement for communication between electronic devices over a communication interconnect. A first group of signals of the...
2016/0147695 FIELD BUS COUPLER FOR CONNECTING INPUT/OUTPUT MODULES TO A FIELD BUS, AND METHOD OF OPERATION FOR A FIELD BUS...
A method and apparatus for operating a field bus coupler in a normal operating mode to connect at least one input/output module with the control computer of an...
2016/0147694 CONNECTOR FOR A COMPUTING ASSEMBLY
Examples disclosed herein provide a computing assembly. The computing assembly includes a first CPU package mounted on a PCB, and a second CPU package mounted...
2016/0147693 MULTICASTING COMPUTER BUS SWITCH
There is disclosed apparatus and methods of multicasting in a shared address space. A shared memory address space may include two or more multicast portions....
2016/0147692 CABLE WITH CIRCUITRY FOR COMMUNICATING PERFORMANCE INFORMATION
A cable with circuitry that enables the cable to communicate data in one of at least two different signal modes of operation is presented. In a first signal...
2016/0147691 KEYBOARD-VIDEO-MOUSE SWITCH AND OPERATING METHOD THEREOF
A keyboard-video-mouse (KVM) switch and an operating method thereof are disclosed. The KVM switch is coupled between at least one peripheral device and...
2016/0147690 INTERFACE SWITCHING APPARATUS
A switching apparatus to adapt an interface for multi-functional use includes a signal source, a display unit, a control unit, and a connector. The signal...
2016/0147689 PROCESSOR APPARATUS WITH PROGRAMMABLE MULTI PORT SERIAL COMMUNICATION INTERCONNECTIONS
A computing and communication chip architecture is provided wherein the interfaces of processor access to the memory chips are implemented as a high-speed...
2016/0147688 METHOD AND APPARATUS FOR PLUG AND PLAY, NETWORKABLE ISO 18000-7 CONNECTIVITY
A device may comprise a Universal Serial Bus (USB) interface and a wireless interface operable to communicate in accordance with the ISO 18000-7 standard. The...
2016/0147687 ARBITRATION IN AN SRIOV ENVIRONMENT
In one embodiment, a computer-implemented method includes assigning a time budget to each of a plurality of virtual functions in a single-root input/output...
2016/0147686 SYNCHRONIZATION OF ELECTRONIC DEVICE WITH ANOTHER ELECTRONIC DEVICE ON BUS USING SYNCHRONIZATION FIELD
Various embodiments are described herein related to techniques for synchronizing a slave device to a master device that communicates using a unified bus...
2016/0147685 ARBITRATION IN AN SRIOV ENVIRONMENT
In one embodiment, a computer-implemented method includes assigning a time budget to each of a plurality of virtual functions in a single-root input/output...
2016/0147684 IN-BAND INTERRUPT TIME STAMP
System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. A method...
2016/0147683 BUS CONTROLLER AND DATA TRANSMISSION METHOD THEREOF
A data transmission method includes: determining a sum of first service proportions and a sum of second service proportions according to a first transmission...
2016/0147682 PROGRAMMABLE CONTROLLER
A programmable controller according to an embodiment includes: a bus for data transmission and reception; a synchronous-control signal line that transmits a...
2016/0147681 DETECTING AND CONFIGURING OF EXTERNAL IO ENCLOSURE
A method, system and computer program product are provided for detecting and configuring an external input/output (IO) enclosure in a computer system. A PCIE...
2016/0147680 INTERRUPTION FACILITY FOR ADJUNCT PROCESSOR QUEUES
Interruption facility for adjunct processor queues. In response to a queue transitioning from a no replies pending state to a reply pending state, an...
2016/0147679 POSTED INTERRUPT ARCHITECTURE
An interrupt is identified from an input/output (I/O) device and an address of a particular cache line is identified associated with the interrupt. The cache...
2016/0147678 METHOD AND APPARATUS FOR SELECTING ONE OF A PLURALITY OF BUS INTERFACE CONFIGURATIONS TO USE
Provided are a method and apparatus for selecting one of a plurality of bus interface configurations to use. Selection is made of a first bus interface...
2016/0147677 INFORMATION PROCESSING DEVICE, I/O SYSTEM, AND I/O CONTROL METHOD
An information processing device that are capable of continuing access to an I/O device by operational computers even when a failure has occurred in a...
2016/0147676 PERIPHERAL COMPONENT INTERCONNECT (PCI) DEVICE AND SYSTEM INCLUDING THE PCI
A peripheral component interconnect (PCI) device includes a PCI register including a base address register (BAR) configured to determine a first memory area...
2016/0147675 ELECTRONIC SYSTEM, ELECTRONIC APPARATUS AND ACCESS AUTHENTICATION METHOD THEREOF
An electronic system, an electronic apparatus, and an access authentication method thereof are provided. The electronic system includes a master apparatus and...
2016/0147674 SYSTEMS AND METHODS FOR PROTECTION OF REFLECTIVE MEMORY SYSTEMS
A computing device within a reflective memory system includes a memory block and a special purpose processor. The memory block includes a plurality of memory...
2016/0147673 MICROCOMPUTER AND METHOD FOR CONTROLLING MEMORY ACCESS
A memory control system includes a memory connected to a memory bus, the memory including a plurality of access areas, a memory controller connected to the...
2016/0147672 DEVICE HAVING MEMORY ACCESS PROTECTION
A device has a protection unit for controlling access to a memory. Indirect memory access requests have control data indicative of a memory access control...
2016/0147671 SYSTEMS AND METHODS OF WRITE CACHE FLUSHING
A data storage device includes a write cache, a non-volatile memory, and a controller coupled to the write cache and to the non-volatile memory. The controller...
2016/0147670 PAGE CACHE DEVICE AND METHOD FOR EFFICIENT MAPPING
Embodiments of the inventive concept can include a multi-stage mapping technique for a page cache controller. For example, a gigantic virtual page address...
2016/0147669 METHOD FOR CONTROLLING ACCESS OF CACHE THROUGH USING PROGRAMMABLE HASHING ADDRESS AND RELATED CACHE CONTROLLER
A method for controlling access of a cache includes at least following steps: receiving a memory address; utilizing a hashing address logic to perform a...
2016/0147668 MEMORY ADDRESS RE-MAPPING OF GRAPHICS DATA
A method and apparatus for creating, updating, and using guest physical address (GPA) to host physical address (HPA) shadow translation tables for translating...
2016/0147667 ADDRESS TRANSLATION IN MEMORY
According to one general aspect, a computational memory may include memory cells configured to store data and a page table, wherein the page table maps, at...
2016/0147666 Multilevel Cache-Based Data Read/Write Method and Apparatus, and Computer System
A multilevel cache-based data read/write method and a computer system. The method includes acquiring a query address of a physical memory data block in which...
2016/0147665 WORKLOAD SELECTION AND CACHE CAPACITY PLANNING FOR A VIRTUAL STORAGE AREA NETWORK
Exemplary methods, apparatuses, and systems receive a first input/output (I/O) trace from a first workload and run the first I/O trace through a cache...
2016/0147664 DYNAMIC PARTIAL BLOCKING OF A CACHE ECC BYPASS
An aspect includes receiving a fetch request for a data block at a cache memory system that includes cache memory that is partitioned into a plurality of cache...
2016/0147663 Graphics Deterministic Pre-Caching
An apparatus includes a computerized appliance having a processor, persistent storage storing one or more executable programs, and Dynamic Random Access Memory...
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