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RF SOI SWITCH WITH BACKSIDE CAVITY AND THE METHOD TO FORM IT
An integrated circuit includes a compound semiconductor substrate having a first semiconductor substrate, an insulating layer on the first semiconductor...
SEMICONDUCTOR MODULE AND POWER CONVERTER
A semiconductor module includes a case, a semiconductor component provided in the case for switching a current, encapsulating resin provided in the case for...
INTEGRATED CIRCUIT PACKAGE WITH EMBEDDED BRIDGE
Embodiments of the present disclosure are directed towards an integrated circuit (IC) package having first and second dies with first and second input/output...
DIFFERENT SCALING RATIO IN FEOL / MOL/ BEOL
In some embodiments, the present disclosure relates to an integrated chip. The integrated chip has a plurality of gate structures arranged over a substrate. A...
Opening Fill Process and Structure Formed Thereby
Methods of forming conductive structures and the conductive structures are disclosed. A method includes forming an opening in a dielectric layer over a...
PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A manufacturing method of a package structure includes the following steps. A substrate including a core layer, first and second patterned metal layers is...
INTERCONNECT STRUCTURE FOR AN INTEGRATED CIRCUIT AND METHOD OF FABRICATING
AN INTERCONNECT STRUCTURE
An integrated circuit includes first and second metallization levels. The first metallization level includes a first metal routing path. The second ...
Decoupling MIM Capacitor Designs for Interposers and Methods of
Decoupling metal-insulator-metal (MIM) capacitor designs for interposers and methods of manufacture thereof are disclosed. In one embodiment, a method of...
MIMCAP STRUCTURE IN A SEMICONDUCTOR DEVICE PACKAGE
The disclosed technology relates generally to a semiconductor device package comprising a metal-insulator-metal capacitor (MIMCAP). In one aspect, the MIMCAP...
METAL-INSULATOR-METAL ON-DIE CAPACITOR WITH PARTIAL VIAS
A Metal-Insulator-Metal on-die capacitor is described with partial vias. In one example, first and second power grid layers are formed in a semiconductor die....
Protrusion Bump Pads for Bond-on-Trace Processing
A die and a substrate are provided. The die comprises at least one integrated circuit chip, and the substrate comprises first and second subsets of conductive...
ETCH BACK PROCESSES OF BONDING MATERIAL FOR THE MANUFACTURE OF
A method for manufacturing vias in a glass substrate includes bonding, through a bonding layer, a first face of the glass substrate including a plurality of...
INTERPOSERS WITH CIRCUIT MODULES ENCAPSULATED BY MOLDABLE MATERIAL IN A
CAVITY, AND METHODS OF FABRICATION
Stacked dies (110) are encapsulated in an interposer's cavity (304) by multiple encapsulant layers (524) formed of moldable material. Conductive paths (520,...
REDUCED PTH PAD FOR ENABLING CORE ROUTING AND SUBSTRATE LAYER COUNT
Embodiments are directed to semiconductor packaging having reduced sized plated through hole (PTH) pads by eliminating the margin of the pad-to-PTH alignment...
ELECTRONIC PACKAGES AND METHODS OF MAKING AND USING THE SAME
An electronic package and a method of making the same in provided. The electronic package includes a dielectric layer and a conformal masking layer disposed on...
SWITCHED POWER STAGE WITH INTEGRATED PASSIVE COMPONENTS
A scalable switching regulator architecture may include an integrated inductor. The integrated inductor may include vias or pillars in a multi-layer substrate,...
MULTI-LAYERED CIRCUIT DEVICE
A multi-layered circuit device includes multiple electrode lines arranged in a plurality of layers. Also included are multiple elements. At least one of the...
SEMICONDUCTOR DEVICE AND MEASUREMENT DEVICE
A semiconductor device includes: an oscillator including external terminals disposed on a first face with a specific distance along a first direction; an...
RESIN-ENCAPSULATED SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
A resin-encapsulated semiconductor device having a semiconductor chip which is prevented from being damaged. The resin-encapsulated semiconductor device (100)...
METHOD FOR PACKAGING A POWER DEVICE WITH BOTTOM SOURCE ELECTRODE
A power semiconductor package has an ultra thin chip with front side molding to reduce substrate resistance; a lead frame unit with grooves located on both...
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes an external lead-out terminal having an external terminal and an internal terminal connected to a connecting portion of the...
SEMICONDUCTOR DEVICES HAVING A TSV, A FRONT-SIDE BUMPING PAD, AND A
BACK-SIDE BUMPING PAD
Semiconductor devices are provided. The semiconductor devices include a substrate, a first interlayer insulating layer disposed on a front-side of the...
THROUGH-SUBSTRATE STRUCTURE AND MEHTOD FOR FABRICATING THE SAME
A method for fabricating through-substrate structure is disclosed. The method includes the steps of: providing a substrate; forming a through-substrate hole...
SEMICONDUCTOR PACKAGING STRUCTURE AND METHOD
A semiconductor packaging method is provided. The method includes providing a semiconductor substrate. The semiconductor substrate has a first surface and a...
SEMICONDUCTOR PACKAGE HAVING HEAT-DISSIPATION MEMBER
A semiconductor package includes a semiconductor chip on a substrate, a thermal conductive film on a lower surface of the semiconductor chip, the thermal...
INTEGRATED HEAT SPREADER THAT MAXIMIZES HEAT TRANSFER FROM A MULTI-CHIP
In at least some embodiments, an electronic package to maximize heat transfer comprises a plurality of components on a substrate. A stiffener plate is...
PACKAGE FOR HIGH-POWER SEMICONDUCTOR DEVICES
Methods and apparatuses for forming a package for high-power semiconductor devices are disclosed herein. A package may include a plurality of distinct thermal...
Semiconductor Package and Method of Fabrication Thereof
A semiconductor package includes a semiconductor chip having a first main face and side faces, an encapsulation covering at least the side faces of the...
ELECTRONIC HARDWARE ASSEMBLY
An electronic hardware assembly including at least a first and second laminar component, wherein the first laminar components includes a die, the die including...
Semiconductor Device and Method for Fabricating Thereof
A semiconductor device and a method of fabricating the same are disclosed. A semiconductor device according to an embodiment of the present invention includes:...
Semiconductor device and method of manufacturing a semiconductor device
Various embodiments provide a semiconductor device, wherein the semiconductor device comprises a semiconductor device chip formed at a substrate, wherein the...
METHODS FOR DEPOSITING FILMS ON SENSITIVE SUBSTRATES
Methods and apparatus to form films on sensitive substrates while preventing damage to the sensitive substrate are provided herein. In certain embodiments,...
VOID MONITORING DEVICE FOR MEASUREMENT OF WAFER TEMPERATURE VARIATIONS
A method of monitoring a temperature of a plurality of regions in a substrate during a deposition process, the monitoring of the temperature including:...
Fabricating a Semiconductor Package with Conductive Carrier
In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the...
SEMICONDUCTOR DEVICE HAVING TUNGSTEN GATE ELECTRODE AND METHOD FOR
FABRICATING THE SAME
The present invention provides a semiconductor device in which the threshold voltage of NMOS and the threshold voltage of PMOS are independently controllable,...
Simultaneous Formation of Source/Drain Openings with Different Profiles
A method includes forming a first gate stack and a second gate stack over a first portion and a second portion, respectively, of a semiconductor substrate,...
Method of Forming a Semiconductor Device
A method of forming a semiconductor device is provided. The method includes forming a recess in a substrate and forming a first dielectric layer in the recess....
MULTI-STAGE FIN FORMATION METHODS AND STRUCTURES THEREOF
A method for fabricating a semiconductor device having a multi-stage fin profile includes providing a substrate and forming a first spacer having a first...
METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
An exemplary method of fabricating a semiconductor device is provided. First and second hard mask patterns adjacent to each other are formed on a substrate....
Germanium FinFETs with Metal Gates and Stressors
An integrated circuit structure includes an n-type fin field effect transistor (FinFET) and a p-type FinFET. The n-type FinFET includes a first germanium fin...
ORGANIC THIN FILM PASSIVATION OF METAL INTERCONNECTIONS
Electronic assemblies and their manufacture are described. One embodiment relates to a method including depositing an organic thin film layer on metal bumps on...
Providing A Chip Die With Electrically Conductive Elements
A method for providing position control information for controlling an impingement position of a laser beam for treatment of a chip die in a chip manufacturing...
3D Integrated Circuit and Methods of Forming the Same
An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous...
Metallization Method for Semiconductor Structures
A method is provided for fabricating a semiconductor device that includes providing a structure with a sacrificial layer having at least one through-hole...
METHOD OF MAKING INTERCONNECT STRUCTURE
A method of making a semiconductor device including forming a first adhesion layer over a substrate. The method further includes forming a second adhesion...
METHOD OF FORMING KEY PATTERNS AND METHOD OF FABRICATING A SEMICONDUCTOR
DEVICE USING THE SAME
Provided are a method of forming key patterns and a method of fabricating a semiconductor device using the same. The method of forming key patterns may include...
CONTACT MODULE FOR OPTIMIZING EMITTER AND CONTACT RESISTANCE
An advanced contact module for optimizing emitter and contact resistance and methods of manufacture are disclosed. The method includes forming a first contact...
METHOD FOR PATTERNING SUB-50-NANOMETERS STRUCTURES
Sub-50-nm structures are formed using sequential top-down and bottom up lithographies in conjunction with selective etching. The preferred rendition of the...
INTERCONNECTION STRUCTURE INCLUDING AIR GAP, SEMICONDUCTOR DEVICE
INCLUDING AIR GAP, AND METHOD OF...
A semiconductor device includes a first insulating layer, a second insulating layer formed on the first insulating layer, a plurality of interconnection lines...
SEMICONDUCTOR WAFER HOLDER AND WAFER CARRYING TOOL USING THE SAME
A wafer holder and a semiconductor wafer carrying tool including the wafer holder are provided. The wafer holder includes a frame portion, a wafer centering...