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Patent # Description
2016/0163634 POWER REDUCED COMPUTING
Systems for performing computing operations in a power-reduced environment include a processor in communication with two data storage media and a...
2016/0163633 DISPLAY PANEL AND DISPLAY DEVICE
A display panel includes a display unit with a first area and a second area, first gate lines on the first area and the second area that extend in a first...
2016/0163632 PACKAGING STRUCTURE AND METHOD OF FABRICATING THE SAME
A package structure includes a dielectric layer having opposing first and second surfaces, a wiring layer formed on the first surface and having a plurality of...
2016/0163631 CHIP CARRIER WITH DUAL-SIDED CHIP ACCESS AND A METHOD FOR TESTING A CHIP USING THE CHIP CARRIER
Disclosed are chip carriers and methods of using them. The chip carriers each comprise a base with a first surface, a second surface opposite the first...
2016/0163630 INTERPOSER WITH EXTRUDED FEED-THROUGH VIAS
A semiconductor device comprises an interposer with extruded feed-through vias and a semiconductor die. The interposers includes a substrate having a plurality...
2016/0163629 SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
A method of fabricating a package structure is provided, including forming a plurality of conductive pillars on a conductive layer, forming an insulating layer...
2016/0163628 PACKAGE SUBSTRATE COMPRISING CAPACITOR, REDISTRIBUTION LAYER AND DISCRETE COAXIAL CONNECTION
A package substrate that includes a first portion and a redistribution portion. The first portion is configured to operate as a capacitor. The first portion...
2016/0163627 INTERPOSER SUBSTRATE AND METHOD OF FABRICATING THE SAME
An interposer substrate includes a first insulating layer having opposite first and second surfaces; a first wiring layer formed in the first insulating layer,...
2016/0163626 INTERPOSER SUBSTRATE AND METHOD OF FABRICATING THE SAME
The invention provides an interposer substrate and a method of fabricating the same. The method includes: etching a carrier to form a recessed groove thereon;...
2016/0163625 SEMICONDUCTOR DEVICE
A semiconductor device includes a wiring substrate having an upper surface, a plurality of terminals formed on the upper surface, and a lower surface opposite...
2016/0163624 PACKAGE STRUCTURE
A package structure includes a chip, a substrate, wires and a molding compound. The chip includes an active surface, a back surface opposite to the active...
2016/0163623 SYSTEM, METHOD AND APPARATUS FOR LEADLESS SURFACE MOUNTED SEMICONDUCTOR PACKAGE
A packaged semiconductor device may include a termination surface having terminations configured as leadless interconnects to be surface mounted to a printed...
2016/0163622 PACKAGING-BEFORE-ETCHING FLIP CHIP 3D SYSTEM-LEVEL METAL CIRCUIT BOARD STRUCTURE AND TECHNIQUE THEREOF
Provided are a packaging-before-etching flip chip 3D system-level metal circuit board structure and technique thereof. The metal circuit board structure...
2016/0163621 SINGLE-LAYER WIRING PACKAGE SUBSTRATE, SINGLE-LAYER WIRING PACKAGE STRUCTURE HAVING THE PACKAGE SUBSTRATE, AND...
A single-layer wiring package substrate and a method of fabricating the same are provided, the method including: forming on a carrier a wiring layer having a...
2016/0163620 STACKED MICROELECTRONIC ASSEMBLY WITH TSVS FORMED IN STAGES AND CARRIER ABOVE CHIP
A microelectronic assembly is provided which includes a first element consisting essentially of at least one of semiconductor or inorganic dielectric material...
2016/0163619 SEMICONDUCTOR CHIP AND STACK TYPE SEMICONDUCTOR APPARATUS USING THE SAME
A semiconductor may include a core block configured to store and output data, and may be configured to output internal information. The semiconductor may...
2016/0163618 HEAT DISSIPATING CIRCUIT BOARD AND ELECTRONIC DEVICE
A heat dissipating circuit board for a power semiconductor includes an electrode material on which a power semiconductor is mounted on a front surface thereof,...
2016/0163617 CERAMIC CIRCUIT BOARD AND ELECTRONIC DEVICE
A ceramic circuit board includes a ceramic substrate, a first metal plate bonded to a front surface of the ceramic substrate, and a member bonded to a front...
2016/0163616 Heat Spreader, Electronic Module Comprising a Heat Spreader and Method of Fabrication Thereof
An electronic module includes a semiconductor package, a heat spreader attached to the semiconductor package and an electrically insulating layer disposed on...
2016/0163615 SEMICONDUCTOR DEVICE
For example, a semiconductor device has a lead connected to a second portion of a chip mounting part on which a semiconductor chip to be a heat source is...
2016/0163614 PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A package structure includes a first substrate, a patterned solder mask, first thermal-conductive posts, a chip and a second substrate. The first substrate...
2016/0163613 ELECTRONIC APPARATUS
An electronic apparatus includes a board, a first electronic component, a mold resin and a second electronic component. The board has a first surface and a...
2016/0163612 SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
The present disclosure relates to semiconductor packages and methods of manufacturing the same. In an embodiment, the semiconductor package includes a...
2016/0163611 LAMINATE SUBSTRATES HAVING RADIAL CUT METALLIC PLANES
A laminate substrate for receiving a semiconductor chip. Included are laminate layers stacked to form the laminate substrate, each laminate layer includes a...
2016/0163610 SEMICONDUCTOR DIE AND PACKAGE JIGSAW SUBMOUNT
A submount for connecting a semiconductor device to an external circuit, the submount comprising: a planar substrate formed from an insulating material and...
2016/0163609 METHODS AND APPARATUS FOR TESTING AUXILIARY COMPONENTS IN A MULTICHIP PACKAGE
Ways for testing a multichip package while reducing the required test pin count are provided. The multichip package may include a main die coupled to multiple...
2016/0163608 SEMICONDUCTOR PACKAGE
A semiconductor package includes a package substrate; a semiconductor chip mounted on a top surface of the package substrate; a chip pad disposed on a bottom...
2016/0163607 SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM AND METHOD OF TESTING SEMICONDUCTOR DEVICE
A semiconductor device may include a semiconductor substrate doped with a first type impurity; a through electrode inserted in the semiconductor substrate; an...
2016/0163606 Generating a Wafer Inspection Process Using Bit Failures and Virtual Inspection
Methods and systems for generating a wafer inspection process are provided. One method includes storing output of detector(s) of an inspection system during...
2016/0163605 SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
A method for fabricating a semiconductor structure is provided. The method includes providing a semiconductor substrate; and forming a plurality of...
2016/0163604 METHODS OF FORMING DIFFUSION BREAKS ON INTEGRATED CIRCUIT PRODUCTS COMPRISED OF FINFET DEVICES AND THE...
One illustrative method disclosed herein includes forming first sacrificial gate structures above a fin for two active gates and a dummy gate, removing the...
2016/0163603 PFET GATE STACK MATERIALS HAVING IMPROVED THRESHOLD VOLTAGE, MOBILITY AND NBTI PERFORMANCE
A method of forming a transistor device includes forming an interfacial layer and a dielectric layer over a substrate; and forming a p-type field effect...
2016/0163602 VERTICAL FIELD EFFECT TRANSISTORS
Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin...
2016/0163601 METHODS OF FORMING REPLACEMENT GATE STRUCTURES FOR SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES
A method that involves forming a high-k gate insulation layer, a work-function adjusting metal layer and a metal protection layer in first and second...
2016/0163600 SELF-ALIGNED QUADRUPLE PATTERNING PROCESS
Methods for modifying a spacer and/or spaces between spacers to enable a fin cut mask to be dropped between the spacers are provided. A first set of second...
2016/0163599 PERFORMANCE OPTIMIZED GATE STRUCTURES
A performance optimized CMOS FET structure and methods of manufacture are disclosed. The method includes forming source and drain regions for a first type...
2016/0163598 METHOD OF FORMING A BICMOS SEMICONDUCTOR CHIP THAT INCREASES THE BETAS OF THE BIPOLAR TRANSISTORS
The betas of the bipolar transistors in a BiCMOS semiconductor structure are increased by forming the emitters of the bipolar transistors with two implants: a...
2016/0163597 WAFER PROCESSING METHOD
A wafer processing method for dividing a wafer into individual device chips along division lines is disclosed. The wafer processing method includes a back...
2016/0163596 PROCESS AND MATERIAL FOR PREVENTING DELETERIOUS EXPANSION OF HIGH ASPECT RATIO COPPER FILLED THROUGH SILICON...
Techniques are disclosed for forming through-silicon vias (TSVs) implementing a negative thermal expansion (NTE) material such as zirconium tungstate...
2016/0163595 METHOD FOR MANUFACTURING THROUGH-HOLE SILICON VIA
A method for manufacturing a through-hole silicon via (TSV) employs the conventional trench insulation process to readily manufacture a through-hole silicon...
2016/0163594 METHOD FOR FORMING VOID-FREE POLYSILICON AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME
A method for fabricating a semiconductor device includes forming a buried gate electrode in a semiconductor substrate. An insulating layer is formed over the...
2016/0163593 METHOD FOR FORMING A SELF-ALIGNED CONTACT IN A DAMASCENE STRUCTURE USED TO FORM A MEMORY DEVICE
Exemplary embodiments of the present invention are directed towards a method for fabricating a self-aligned contact under a bitline in a damascene structure...
2016/0163592 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
In a method for manufacturing a semiconductor, a Through Silicon Via (TSV) template wafer and production wafers form a sandwich structure, in which the TSV...
2016/0163591 COPPER WIRING FORMING METHOD, FILM FORMING SYSTEM, AND STORAGE MEDIUM
A Cu wiring forming method of forming Cu wiring that is to be arranged in contact with tungsten wiring, by filling Cu into a recess formed in a substrate,...
2016/0163590 METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
Disclosed is a method of manufacturing a semiconductor device. A preliminary wafer-carrier assembly is formed in such a way that a wafer structure having a...
2016/0163589 METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING CONDUCTIVE STRUCTURES
A method of forming a semiconductor device can include forming an insulation layer using a material having a composition selected to provide resistance to...
2016/0163588 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
The present invention relates to a semiconductor device and a method for manufacturing the same. Disclosed is a semiconductor device including a substrate, a...
2016/0163587 SELF-ALIGNED VIA INTERCONNECT STRUCTURES
A self-aligned via interconnect structures and methods of manufacturing thereof are disclosed. The method includes forming a wiring structure in a dielectric...
2016/0163586 METHODS OF FABRICATING A SEMICONDUCTOR DEVICE HAVING A VIA STRUCTURE AND AN INTERCONNECTION STRUCTURE
Methods of fabricating a semiconductor device include forming a lower interlayer insulating layer and a conductive base structure, forming a middle interlayer...
2016/0163585 METHODS OF FORMING SELF-ALIGNED CONTACT STRUCTURES ON SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES
One method disclosed includes, among other things, forming a structure comprised of an island of a first insulating material positioned between the gate...
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