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Patent # Description
2016/0162433 IO-LINK ADAPTER
An IO-Link adapter (200) for connecting a field device to a master unit having an IO-Link interface (210), a field device interface (220) and a circuit...
2016/0162432 SYSTEM AND METHOD FOR REDUCING CROSS COUPLING EFFECTS
A device includes a first driver circuit coupled to a first bus line, where the first driver circuit includes a first delay element. The first delay element is...
2016/0162431 ELECTRONIC DEVICE WITH MULTIPLE INTERFACES
An electronic device with multiple interfaces includes at least two interfaces, a memory, and a controller. The memory stores a first operation setting...
2016/0162430 INTEGRATED CIRCUITS WITH UNIVERSAL SERIAL BUS 2.0 AND EMBEDDED UNIVERSAL SERIAL BUS 2 CONNECTIVITY
An integrated circuit is provided. The integrated circuit includes a communication-mode determination circuitry configured to detect a signal level at one or...
2016/0162429 SYSTEM AND METHOD FOR NON-UNICAST/DESINTATION LOOKUP FAIL (DLF) LOAD BALANCING
Aspects of the present invention include a port extender environment using the port extenders to dynamically select a data path. In embodiments of the present...
2016/0162428 Operation of a Switch in Linear Mode
Examples disclose a computing device comprising a switch to operate in a linear mode according to a threshold. The switch operates in the linear mode based on...
2016/0162427 INTEGRATED SYSTEMS WITH UNIVERSAL SERIAL BUS 2.0 AND EMBEDDED UNIVERSAL SERIAL BUS 2 CONNECTIVITY
An integrated circuit is provided. The integrated circuit includes a mapping circuit configured to determine a state associated with a first universal series...
2016/0162426 OPTIMAL SAMPLING OF DATA-BUS SIGNALS USING CONFIGURABLE INDIVIDUAL TIME DELAYS
A method includes receiving a group of logic signals to be sampled at a common sampling timing. Individual time delays, which individually align each of the...
2016/0162425 ASSOCIATING PROCESS PRIORITY WITH I/O QUEUING
Described herein is a system and method for associating process priority with I/O queuing. The system can receive a first I/O request from a first process;...
2016/0162424 MULTIPROCESSOR SYSTEM WITH IMPROVED SECONDARY INTERCONNECTION NETWORK
Embodiments of a multiprocessor system are disclosed that may include a plurality of processors interspersed with a plurality of data memory routers, a...
2016/0162423 N-PHASE SIGNAL TRANSITION ALIGNMENT
System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information...
2016/0162422 DUAL ACCESS MEMORY MAPPED DATA STRUCTURE MEMORY
Systems and methods are provided for expanding the available memory of a storage controller. The systems and methods utilize a PCIe memory controller connected...
2016/0162421 LTR/OBFF DESIGN SCHEME FOR ETHERNET ADAPTER APPLICATION
A method of reducing power consumption in a computing platform is disclosed. An endpoint-device that is coupled to the computing platform includes a first data...
2016/0162420 INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND RECORDING MEDIUM
A deletion instruction of data stored in a nonvolatile memory is input, a determination is made whether the nonvolatile memory has reached an end of its...
2016/0162419 Methods and Systems for Protecting Data in USB Systems
The various embodiments described below are directed to providing authenticated and confidential messaging from software executing on a host (e.g. a secure...
2016/0162418 INFORMATION PROCESSING APPARATUS CAPABLE OF BACKING UP AND RESTORING KEY FOR DATA ENCRYPTION AND METHOD FOR...
An information processing apparatus includes a storage device configured to store data, an encryption chip configured to store an encryption key therein, a...
2016/0162417 STORING DATA IN A SERVER COMPUTER WITH DEPLOYABLE ENCRYPTION/DECRYPTION INFRASTRUCTURE
For storing data in a data-storage structure of a server computer, an infrastructure is deployed to a server computer. The infrastructure has a forwarder...
2016/0162416 Apparatus and Method for Reducing Latency Between Host and a Storage Device
Described is a system comprising: a storage device; a bus; and a host apparatus including a host memory and a driver module, wherein the host apparatus is...
2016/0162415 SYSTEMS AND METHODS FOR PROVIDING IMPROVED LATENCY IN A NON-UNIFORM MEMORY ARCHITECTURE
Systems, methods, and computer programs are disclosed for allocating memory in a portable computing device having a non-uniform memory architecture. One...
2016/0162414 CACHING AND DEDUPLICATION OF DATA BLOCKS IN CACHE MEMORY
Techniques for deduplicating data in cache memory include determining that a first data block stored in the cache memory matches a second data block stored in...
2016/0162413 Application Startup Page Fault Management in a Hardware Multithreading Environment
A method, system and computer-usable medium are disclosed for startup page fault management improves application startup performance by assigning startup tasks...
2016/0162412 COMPLETION PACKET RETURN
A completion packet may be returned before a data packet is written to a memory, if a field of the data packet indicates the data packet was sent due to a...
2016/0162411 Invalidating a Range of Two or More Translation Table Entries and Instruction Therefore
An instruction is provided to perform invalidation of an instruction specified range of segment table entries or region table entries. The instruction can be...
2016/0162410 DEMOTE INSTRUCTION FOR RELINQUISHING CACHE LINE OWNERSHIP
A computer system processor of a multi-processor computer system having a cache subsystem, the computer system having exclusive ownership of a cache line,...
2016/0162409 VIRTUAL MACHINE HOST SERVER APPARATUS AND METHOD FOR OPERATING THE SAME
A virtual machine host server includes a virtual machine in which a guest operating system is installed and operated, a cache manager for processing at least...
2016/0162408 PARALLEL DESTAGING WITH REPLICATED CACHE PINNING
Methods, apparatus and computer program products implement embodiments of the present invention that include identifying non-destaged first data in a write...
2016/0162407 MULTICORE, MULTIBANK, FULLY CONCURRENT COHERENCE CONTROLLER
This invention optimizes non-shared accesses and avoids dependencies across coherent endpoints to ensure bandwidth across the system even when sharing. The...
2016/0162406 Systems, Methods, and Apparatuses to Decompose a Sequential Program Into Multiple Threads, Execute Said...
Systems, methods, and apparatuses for decomposing a sequential program into multiple threads, executing these threads, and reconstructing the sequential...
2016/0162405 CACHING OF DATA IN DATA STORAGE SYSTEMS BY MANAGING THE SIZE OF READ AND WRITE CACHE BASED ON A MEASUREMENT OF...
A disk drive is disclosed that varies its caching policy for caching data in non-volatile solid-state memory as the memory degrades. As the non-volatile memory...
2016/0162404 MEMORY MODULE WITH LOCAL SYNCHRONIZATION
A memory module is operatable in a memory system with a memory controller. The memory module comprises a module control device to receive command signals from...
2016/0162403 PROGRAMMING NON-VOLATILE MEMORY USING A RELAXED DWELL TIME
In at least one embodiment, a data storage system includes a non-volatile memory array including a plurality of blocks of physical memory, each including...
2016/0162402 INDIRECTLY ACCESSING SAMPLE DATA TO PERFORM MULTI-CONVOLUTION OPERATIONS IN A PARALLEL PROCESSING SYSTEM
In one embodiment of the present invention, a convolution engine configures a parallel processing pipeline to perform multi-convolution operations. More...
2016/0162401 ALIGNMENT BASED BLOCK CONCURRENCY FOR ACCESSING MEMORY
Embodiments relate to accessing data in a memory. A method for accessing data in a memory coupled to a processor is provided. The method receives a memory...
2016/0162400 ALIGNMENT BASED BLOCK CONCURRENCY FOR ACCESSING MEMORY
Embodiments relate to accessing data in a memory. A method for accessing data in a memory coupled to a processor is provided. The method receives a memory...
2016/0162399 SYSTEMS AND METHODS FOR PROVIDING IMPROVED LATENCY IN A NON-UNIFORM MEMORY ARCHITECTURE
Systems, methods, and computer programs are disclosed for allocating memory in a portable computing device having a non-uniform memory architecture. One...
2016/0162398 AUTOMATED TEST GENERATION AND EXECUTION FOR TESTING A PROCESS TO CONTROL A COMPUTER SYSTEM
User interactions with a computing system are sensed and recorded. The recording represents a process for controlling a computer system. The computer system...
2016/0162397 Testing Coordinator
A system for testing two or more applications associated with a computerized process may include a central repository, a user interface and a testing...
2016/0162396 UPDATING SOFTWARE
This invention relates to a method and apparatus for updating software. In particular this invention relates to a method, system and computer program for...
2016/0162395 SOFTWARE TESTING OPTIMIZER
In an approach for testing software, a computer receives a series of two or more revisions to a set of software code. The computer identifies modifications...
2016/0162394 SOFTWARE TESTING OPTIMIZER
In an approach for testing software, a computer receives a series of two or more revisions to a set of software code. The computer identifies modifications...
2016/0162393 Testing Coordinator
A system for testing two or more applications associated with a computerized process may include a central repository, a user interface and a testing...
2016/0162392 Adaptive Framework Automatically Prioritizing Software Test Cases
An automated, self-adaptive framework prioritizes software testing in a consistent and effective manner. A metric evaluates past test execution information for...
2016/0162391 APPLICATION DEVELOPMENT VIA A MULTI-UNIT DEVICE
Disclosed are various embodiments for systems and methods to provide to a processor unit over a network. The processor unit may be used for testing ...
2016/0162390 ORTHOGONAL EXPERIMENTATION IN A COMPUTING ENVIRONMENT
Various embodiments include at least one of systems, methods, and software to receive input configuring tests within a computing environment to expose users to...
2016/0162389 Device Cloud Monitoring and Stability
An example system may include a first device connected over respective communications interfaces to a plurality of second devices. The first device may...
2016/0162388 TRANSITIVE SOURCE CODE VIOLATION MATCHING AND ATTRIBUTION
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for matching and attributing code violations. One of the...
2016/0162387 PROMOTION DETERMINATION BASED ON AGGREGATED CODE COVERAGE METRICS
Techniques are described for aggregating code coverage data generated from various types of testing of software modules, and automatically determining whether...
2016/0162386 CODE CHANGE ANALYSIS TO OPTIMIZE TESTING LIFECYCLE
The present disclosure relates to system(s) and method(s) for detecting change in software code of elements in a current version associated with a software...
2016/0162385 CORRELATION OF VIOLATING CHANGE SETS IN REGRESSION TESTING OF COMPUTER SOFTWARE
Embodiments of the invention provide for the correlation of violating change sets during regression testing of a computer program. A method of the invention...
2016/0162384 APPARATUS AND PROGRAM
This apparatus is provided with a storage means and a comparison means. The storage means has two or more modules stored therein. The comparison means...
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