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Patent # Description
2016/0173151 RECEIVING DEVICE, COMMUNICATION SYSTEM, AND INTERFERENCE DETECTION METHOD
A receiving device of an embodiment has a receiver, a demultiplexer, and an interference detector. The receiver receives a multiplexed signal. The ...
2016/0173150 METHOD FOR NOISE POWER ESTIMATION
Described herein are technologies related to an implementation of noise power estimation in a receiver of a device.
2016/0173149 Automatic Twist and Sway Compensation in a Microwave Backhaul Transceiver
A first microwave backhaul transceiver may comprise an antenna array and circuitry. The circuitry may determine misalignment of the first microwave backhaul...
2016/0173148 MITIGATING SIGNAL INTERFERENCE IN A WIRELESS NETWORK
A method, communication apparatus, and computer program product is provided for mitigating interference experienced by a wireless communication device, WCD...
2016/0173147 DISTORTION COMPENSATION DEVICE AND DISTORTION COMPENSATION METHOD
A distortion compensation device includes: a storage configured to store a distortion compensation coefficient for compensating a distortion of a transmission...
2016/0173146 APPARATUS AND METHOD FOR CONTROLLING GAIN IN COMMUNICATION SYSTEM
A method and a terminal are provided for use in a communication system. The method includes determining an average power from power obtained in a measurement...
2016/0173145 LOW NOISE AMPLIFIER PROVIDING VARIABLE GAINS AND NOISE CANCELLATION FOR CARRIER AGGREGATION
A variable-gain, low noise amplifier system includes a variable-gain, low noise amplifier, having a matching stage, coupled to an input signal with a plurality...
2016/0173144 SYSTEMS AND METHODS OF RF POWER TRANSMISSION, MODULATION, AND AMPLIFICATION
An apparatus, system, and method are provided for energy conversion. For example, the apparatus can include a trans-impedance node, a reactive element, and a...
2016/0173143 APPARATUS FOR TRANSMITTING AND RECEIVING SIGNALS IN RADIO FREQUENCY SYSTEM
An apparatus for receiving signals in a radio frequency system includes a low noise amplifier that amplifies and filters a signal received from an antenna; a...
2016/0173142 COMMON MODE NOISE INTRODUCTION TO REDUCE RADIO FREQUENCY INTERFERENCE
Techniques for noise reduction are described herein. The techniques include an apparatus for noise reduction including a voltage tuner to adjust a voltage...
2016/0173141 METHOD OF CONTROLLING UPLINK NOISE LEVEL IN MULTI-RU ENVIRONMENT
Provided is a method of controlling an uplink noise level in a multi-radio unit (RU) environment in which each RU measures an ordinary noise level using a...
2016/0173140 METHOD AND APPARATUS FOR AN ANTENNA
There are disclosed various methods and apparatuses for an antenna. In some embodiments of the method a transmission signal is provided to a first feed point...
2016/0173139 AVIONIC INFORMATION TRANSMISSION SYSTEM
This system for transmitting avionic information of the type including means for transmitting data frames through at least one transmission network based on...
2016/0173138 DEVICE FOR BI-DIRECTIONAL AND MULTI-BAND RF COMMUNICATION OVER SINGLE RESONANT TRANSMISSION LINE AND METHOD OF...
A duplexing system including: a duplexer; an antenna capable of transmitting and receiving electromagnetic signals; a transmitter adapted to couple...
2016/0173137 RECEIVER AND VOLTAGE CONTROLLED OSCILLATOR
According to an embodiment, a receiver includes a voltage controlled oscillator, a frequency-to--digital converter and an input sensitivity controller. In the...
2016/0173136 DYNAMIC ADJUSTMENT OF DATA PROTECTION SCHEMES IN FLASH STORAGE SYSTEMS BASED ON TEMPERATURE, POWER OFF DURATION...
A data retention methodology for use in electrically rewritable nonvolatile storage systems is disclosed. The methodology collects characteristic data of the...
2016/0173135 TRANSMITTER AND SIGNAL PROCESSING METHOD THEREOF
A transmitter is provided, which includes: an encoder configured to generate a low density parity check (LDPC) codeword comprising information word bits, first...
2016/0173134 Enhanced Data Bus Invert Encoding for OR Chained Buses
Methods and apparatus relating to enhanced Data Bus Invert (EDBI) encoding for OR chained buses are described. In an embodiment, incoming data on a bus is...
2016/0173133 METHOD AND DATA PROCESSING DEVICE FOR DETERMINING AN ERROR VECTOR IN A DATA WORD
In various embodiments, a method for determining an error vector in a data word is provided. The method includes determining the syndrome of the error vector,...
2016/0173132 Construction of Structured LDPC Convolutional Codes
Protograph construction methods for generating convolutional LDPC code matrices are disclosed in which multi-equation problems of girth maximization are...
2016/0173131 Method and Apparatus of a Fully-Pipelined Layered LDPC Decoder
Processors are arranged in a pipeline structure to operate on multiple layers of data, each layer comprising multiple groups of data. An input to a memory is...
2016/0173130 EARLY DECODE ATTEMPT OF LOWER RATE LTE CODE BLOCKS THAT ARE REPEAT COMBINED MULTIPLE TIMES
A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus receives configuration information indicating a...
2016/0173129 LDPC CODE MATRICES
An LDPC parity check matrix, includes a systematic portion having a plurality of systematic elements and a parity portion having a plurality of parity...
2016/0173128 MEMORY CONTROLLER AND METHOD OF DATA BUS INVERSION USING AN ERROR DETECTION CORRECTION CODE
Memory controllers, devices and associated methods are disclosed. In one embodiment, a memory controller includes write circuitry to transmit write data to a...
2016/0173127 DATA COMPRESSION APPARATUS AND METHOD
A data compression apparatus includes a memory and a processor. The processor extracts a second character string as a matching string from a character string...
2016/0173126 TECHNIQUES TO ACCELERATE LOSSLESS COMPRESSION
An embodiment may include circuitry that may be capable of performing compression-related operations that may include: (a) indicating, at least in part, in a...
2016/0173125 SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF
Disclosed is an operating method of a semiconductor device, including acquiring resource information on a plurality of hardware resources, receiving a...
2016/0173124 SYSTEM AND METHOD OF COMBINATORIAL HYPERMAP BASED DATA REPRESENTATIONS AND OPERATIONS
A method and apparatus is provided for implementing combinatorial hypermaps (CHYMAPS) and/or generalized combinatorial maps (G-Maps) based data representations...
2016/0173123 PARTITIONED DATA COMPRESSION USING ACCELERATOR
In an embodiment, a processor includes a compression accelerator coupled to a plurality of hardware processing cores. The compression accelerator is to:...
2016/0173122 System That Reconfigures Usage of a Storage Device and Method Thereof
In one embodiment, the invention presented herein relates to a system that reconfigures usage of a storage device. The system includes an apparatus, a sensor...
2016/0173121 CIRCUIT GENERATING AN ANALOG SIGNAL USING A PART OF A SIGMA-DELTA ADC
The circuit generates an analog output signal which may be used to test a sigma-delta ADC. A digital waveform generator supplies a digital signal to a DAC to...
2016/0173120 TEST SIGNAL GENERATOR FOR SIGMA-DELTA ADC
The test signal generator generates an analog and digital test signals to test a sigma-delta ADC which has an analog portion succeeded by a digital decimation...
2016/0173119 INJECTION LOCKED RING OSCILLATOR BASED DIGITAL-TO-TIME CONVERTER AND METHOD FOR PROVIDING A FILTERED...
Apparatus and methods for a digital-to-time converter (DTC) are provided. In an example, a DTC can include a phase interpolator and a ring oscillator. The...
2016/0173118 PREDICTIVE TIME-TO-DIGITAL CONVERTER AND METHOD FOR PROVIDING A DIGITAL REPRESENTATION OF A TIME INTERVAL
Predictive time-to-digital converters (TDCs) and methods for providing a digital representation of a time interval are disclosed herein. In an example, a TDC...
2016/0173117 METHOD AND SYSTEM FOR BROADBAND ANALOG TO DIGITAL CONVERTER TECHNOLOGY
Methods and systems are provided for reconstructing bands in received signals. A first band in a received multiband signal may be reconstructed, during...
2016/0173116 CIRCUIT CALIBRATING METHOD AND CIRCUIT CALIBRATING SYSTEM
A circuit calibrating method, applied to an ACS generating circuit, which comprises a plurality of ACS generating units and activates the ACS generating unit...
2016/0173115 PASSIVE AMPLIFICATION CIRCUIT AND ANALOG-DIGITAL CONVERTOR
A differential signal is amplified by passive amplification which does not a reference of a common-mode voltage. At this time, the voltage of the differential...
2016/0173114 A/D CONVERTER AND A/D CONVERTER CALIBRATING METHOD
An A/D converter includes an A/D conversion unit, a histogram generation-storage unit, and a control unit. The A/D conversion unit is configured to receive an...
2016/0173113 N-PATH CASCODE TRANSISTOR OUTPUT SWITCH FOR A DIGITAL TO ANALOG CONVERTER
Techniques are provided for a switched output digital to analog converter employing an N-path cascode output switch. An example system may include a plurality...
2016/0173112 SWITCHABLE SECONDARY PLAYBACK PATH
In accordance with embodiments of the present disclosure, a processing system may include a plurality of processing paths including a first processing path and...
2016/0173111 MODIFIED DELTA-SIGMA MODULATOR FOR PHASE COHERENT FREQUENCY SYNTHESIS APPLICATIONS
A phase coherent fractional-N phase-locked loop synthesizer for maintaining phase coherence of a synthesized frequency includes a phase coherent delta-sigma...
2016/0173110 SEMICONDUCTOR DEVICE AND CLOCK CORRECTION METHOD
A frequency error calculator includes a first logic circuit that receives a control signal and a clock, a second logic circuit that receives the control signal...
2016/0173109 XOR PHASE DETECTOR, PHASE-LOCKED LOOP, AND METHOD OF OPERATING A PLL
An XOR phase detector for a phase-locked loop PLL comprises an XOR gate which has an input for a periodic reference signal and another input connected to a...
2016/0173108 SEMICONDUCTOR DEVICE
A delay time is set only within the variable delay time of a clock driver and cannot be set longer than the variable delay time of the clock driver. A control...
2016/0173107 CLOCK DATA RECOVERY CIRCUIT AND SEMICONDUCTOR DEVICE
A clock data recovery circuit is configured to receive an input data signal formed of a series of input data pieces synchronized with a reference clock signal,...
2016/0173106 LOW POWER DIGITAL SELF-GATED BINARY COUNTER
An n-bit counter is formed from cascading counter sub-modules. The counter includes combinatorial control logic coupled to a lower-order counter sub-module....
2016/0173105 PRINTED CIRCUIT BOARD SECURITY USING EMBEDDED PHOTODETECTOR CIRCUIT
Systems and methods to obstruct analysis of a microchip may include an electrical component of a microchip and a photodetector positioned within the microchip....
2016/0173104 PROGRAMMABLE FORWARDING PLANE
A forwarding plane comprising a scalable array of field programmable gate array (FPGA) devices, a memory bank, FPGA data and transport network ports, and an...
2016/0173103 SPACE-MULTIPLEXING DRAM-BASED RECONFIGURABLE LOGIC
According to one general aspect, an apparatus may include a random access memory array that, in turn, includes a reconfigurable look-up table. The ...
2016/0173102 DRAM-BASED RECONFIGURABLE LOGIC
According to one general aspect, an apparatus may include a memory array comprising a plurality of memory sub-arrays. At least one of the sub-arrays may be...
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