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Patent # Description
2016/0172499 SEMICONDUCTOR DEVICE
A semiconductor device includes a gate electrode having a first side wall at an end thereof, a gate insulating layer on a top surface and the first side wall...
2016/0172498 FINFET WITH EPITAXIAL SOURCE AND DRAIN REGIONS AND DIELECTRIC ISOLATED CHANNEL REGION
A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least...
2016/0172497 METHOD TO INDUCE STRAIN IN 3-D MICROFABRICATED STRUCTURES
Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over...
2016/0172496 FINFET TRANSISTOR WITH EPITAXIAL STRUCTURES
A field effect transistor with epitaxial structures includes a fin-shaped structure and a metal gate across the fin-shaped structure. The metal gate includes a...
2016/0172495 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor structure is provided, comprising a substrate (130), a support structure (131), a base region (100), a gate stack, a spacer (240), and a...
2016/0172494 MEMORY CELL ARRAY AND CELL STRUCTURE THEREOF
A memory device includes a substrate and a memory array. The substrate has a continuous active region. The memory array is disposed in the continuous active...
2016/0172493 INTEGRATED CIRCUITS WITH DUAL SILICIDE CONTACTS AND METHODS FOR FABRICATING SAME
Integrated circuits having silicide contacts with reduced contact resistance and methods for fabricating integrated circuits having silicide contacts with...
2016/0172492 METHOD FOR DEPINNING THE FERMI LEVEL OF A SEMICONDUCTOR AT AN ELECTRICAL JUNCTION AND DEVICES INCORPORATING...
An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.
2016/0172491 METHOD FOR DEPINNING THE FERMI LEVEL OF A SEMICONDUCTOR AT AN ELECTRICAL JUNCTION AND DEVICES INCORPORATING...
An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.
2016/0172490 HIGH- VOLTAGE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
The present disclosure provides a high-voltage semiconductor device, including: a substrate; an epitaxial layer disposed over the substrate and having a first...
2016/0172489 SEMICONDUCTOR DEVICE AND RELATED FABRICATION METHODS
Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a body well region having a...
2016/0172488 SEMICONDUCTOR DEVICE HAVING DUAL WORK FUNCTION GATE STRUCTURE, METHOD FOR FABRICATING THE SAME, TRANSISTOR...
A semiconductor device including a substrate in which a trench is formed, a first impurity region and a second impurity region formed in the substrate...
2016/0172487 METHOD AND APPARATUS FOR POWER DEVICE WITH MULTIPLE DOPED REGIONS
A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source...
2016/0172486 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor substrate having a first conductivity type, an epitaxial layer having a second conductivity type, an isolation...
2016/0172485 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor substrate and a semiconductor element arranged on a predetermined surface side of the semiconductor substrate....
2016/0172484 Vertical FET Having Reduced On-Resistance
In one implementation, a vertical field-effect transistor (FET) includes a substrate having a drift region situated over a drain, a body region situated over...
2016/0172483 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
The present inventive concept relates to a semiconductor device, and more particularly to a semiconductor device that can increase the amount of current by...
2016/0172482 INTEGRATING ENHANCEMENT MODE DEPLETED ACCUMULATION/INVERSION CHANNEL DEVICES WITH MOSFETS
A plurality of gate trenches is formed into an epitaxial region of a first conductivity type over a semiconductor substrate. One or more contact trenches are...
2016/0172481 SILICON CARBIDE SEMICONDUCTOR DEVICES
Methods, systems, and devices are disclosed for thermal processing of silicon carbide semiconductor devices. In one aspect, a method for fabricating a silicon...
2016/0172480 GATE STRUCTURES FOR III-N DEVICES
A semiconductor device includes a III-N layer, a plurality of parallel conductive fingers on the III-N layer, an insulator layer over the III-N layer, and a...
2016/0172479 METHODS AND SYSTEMS FOR ULTRA-HIGH QUALITY GATED HYBRID DEVICES AND SENSORS
High electron mobility leads to better device performance and today is achieved by fabricating "gated devices" within a high-mobility two-dimensional electron...
2016/0172478 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device includes: a buffer layer formed over a substrate; a first semiconductor layer formed over the buffer layer by using a compound...
2016/0172477 METHODS TO ACHIEVE HIGH MOBILITY IN CLADDED III-V CHANNEL MATERIALS
An apparatus including a heterostructure disposed on a substrate and defining a channel region, the heterostructure including a first material having a first...
2016/0172476 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
A semiconductor device includes a first semiconductor layer formed on a substrate; a second semiconductor layer and a third semiconductor layer formed on the...
2016/0172475 METHOD OF FORMING A SEMICONDUCTOR STRUCTURE
A semiconductor structure comprises a first layer. The first layer comprises a first III-V semiconductor material. The semiconductor structure also comprises a...
2016/0172474 Semiconductor Device and Method of Manufacturing Semiconductor Device
A semiconductor device includes a buffer layer, a channel layer, a barrier layer, and agate electrode over a substrate, the gate electrode being disposed in a...
2016/0172473 NITRIDE SEMICONDUCTOR DEVICE COMPRISING NITRIDE SEMICONDUCTOR REGROWTH LAYER
A nitride semiconductor device according to one embodiment of the present disclosure includes: a substrate; a first nitride semiconductor layer supported by...
2016/0172472 TECHNIQUES FOR FORMING NON-PLANAR GERMANIUM QUANTUM WELL DEVICES
Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV...
2016/0172471 REVERSE CONDUCTING INSULATED GATE BIPOLAR TRANSISTOR
A semiconductor layer of a reverse conducting insulated gate bipolar transistor is provided with a barrier region of the first conductive type, wherein the...
2016/0172470 Isolation Structure of Fin Field Effect Transistor
A representative fin field effect transistor (FinFET) includes a substrate having a major surface; a fin structure protruding from the major surface having a...
2016/0172469 SiGe FINFET WITH IMPROVED JUNCTION DOPING CONTROL
A semiconductor device and a method for fabricating the device. The method includes: providing a FinFET having a source/drain region, at least one SiGe fin, a...
2016/0172468 METHOD OF FORMING A SILICON-CARBIDE DEVICE WITH A SHIELDED GATE
A silicon-carbide semiconductor substrate having a plurality of first doped regions being laterally spaced apart from one another and beneath a main surface,...
2016/0172467 REPLACEMENT METAL GATE INCLUDING DIELECTRIC GATE MATERIAL
A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation...
2016/0172466 METHOD TO REDUCE ETCH VARIATION USING ION IMPLANTATION
The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor...
2016/0172465 PLANAR III-V FIELD EFFECT TRANSISTOR (FET) ON DIELECTRIC LAYER
A method of forming a semiconductor substrate including a type III-V semiconductor material directly on a dielectric material that includes forming a trench in...
2016/0172464 ELECTRONIC DEVICE HAVING AN ELECTRONIC COMPONENT AND A PROCESS OF FORMING THE SAME
In an embodiment, a process of forming an electronic device can include providing a semiconductor substrate having a first major side and an electronic...
2016/0172463 METAL-INSULATOR-METAL DIODES AND METHODS OF FABRICATION
Provided herein are embodiments relating to metal-insulator-metal diodes and their method of manufacture. In some embodiments, the metal-insulator-metal diodes...
2016/0172462 FIN REPLACEMENT IN A FIELD-EFFECT TRANSISTOR
In a method for fabricating a field-effect transistor (FET) structure, forming a fin on a semiconductor substrate. The method further includes forming a gate...
2016/0172461 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device includes: a plurality of n type pillar regions and an n- type epitaxial layer disposed on a first surface of an n++ type silicon carbide...
2016/0172460 FINFET SPACER WITHOUT SUBSTRATE GOUGING OR SPACER FOOT
The present invention relates generally to semiconductor devices, and more particularly, to a structure and method of forming a spacer adjacent to a gate in a...
2016/0172459 ACTIVE REGIONS WITH COMPATIBLE DIELECTRIC LAYERS
A method to form a semiconductor structure with an active region and a compatible dielectric layer is described. In one embodiment, a semiconductor structure...
2016/0172458 SCHOTTKY DEVICE AND METHOD OF MANUFACTURE
A Schottky device includes a barrier height adjustment layer in a portion of a semiconductor material. In accordance with an embodiment, the Schottky device is...
2016/0172457 METHODS OF FABRICATING SILICON NANOWIRES AND DEVICES CONTAINING SILICON NANOWIRES
The present disclosure relates to a method of fabricating a silicon nanowire having a width of 100 nm or less, especially 50 nm or less, by depositing a metal...
2016/0172456 HIGH RESISTANCE METAL ETCH-STOP PLATE FOR METAL FLYOVER LAYER
A semiconductor device includes a transistor having a metal gate, a source, and a drain. The semiconductor device also includes a high resistance metal...
2016/0172455 RECESSED OHMIC CONTACTS IN A III-N DEVICE
A device includes a III-N layer having an upper side and a lower side, the lower side being opposite the upper side, and at least one conductive contact on the...
2016/0172454 Reliable and Robust Electrical Contact
In one implementation, a reliable and robust electrical contact includes a contact pad patterned from a first metal layer situated over a surface of an active...
2016/0172453 REVERSE CONDUCTING INSULATED GATE BIPOLAR TRANSISTOR
A semiconductor layer of a reverse conducting insulated gate bipolar transistor is provided with a drift region of a first conductive type, a body region of a...
2016/0172452 LATERAL DEVICES CONTAINING PERMANENT CHARGE
A lateral device includes a gate region connected to a drain region by a drift layer. An insulation region adjoins the drift layer between the gate region and...
2016/0172451 SEMICONDUCTOR ARRANGEMENT
A semiconductor arrangement comprising a substrate having a first trench formed therein, a field plate layer arranged to extend within the first trench and...
2016/0172450 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
The present disclosure relates to a semiconductor device including an oxygen gettering layer between a group III-V compound semiconductor layer and a...
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