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Patent # Description
2016/0172299 INTEGRATED DEVICE PACKAGE COMPRISING PHOTO SENSITIVE FILL BETWEEN A SUBSTRATE AND A DIE
An integrated device package that includes a die, a substrate, a fill and a conductive interconnect. The die includes a pillar, where the pillar has a first...
2016/0172298 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
A semiconductor device includes an interlayer insulating film INS2, adjacent Cu wirings M1W formed in the interlayer insulating film INS2, and an insulating...
2016/0172297 DESIGNED-BASED INTERCONNECT STRUCTURE IN SEMICONDUCTOR STRUCTURE
Semiconductor structures are provided. The semiconductor structure includes a plurality of gate structures extending in a first direction formed over a...
2016/0172296 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A method for manufacturing a semiconductor device includes forming a conductive pattern on a substrate, forming a filling insulation layer covering the...
2016/0172295 Power FET Having Reduced Gate Resistance
In one implementation, a power field-effect transistor (FET) having a reduced gate resistance includes a drain, a source, a gate, and a gate contact including...
2016/0172294 HIGH ASPECT RATIO STRUCTURE
A high aspect ratio structure is provided. The high aspect ratio structure includes a substrate, a plurality of stack structures, and a plurality of support...
2016/0172293 INTERPOSER WITH SIGNAL-CONDITIONED EDGE PROBE POINTS
An interposer comprising an array of top contacts on the top surface configured to interface with an integrated circuit package, a corresponding array of...
2016/0172292 SEMICONDUCTOR PACKAGE ASSEMBLY
The invention provides a semiconductor package assembly. The semiconductor package assembly includes a substrate structure having a cavity. A bottom surface of...
2016/0172291 SEMICONDUCTOR PACKAGE
A semiconductor package may include a package substrate with a top surface and a bottom surface opposite to the top surface, the top surface of the package...
2016/0172290 INTERPOSER WITH LATTICE CONSTRUCTION AND EMBEDDED CONDUCTIVE METAL STRUCTURES
A lattice structure is formed in a non-silicon interposer substrate to create large cells that are multiples of through hole pitches to act as islands for...
2016/0172289 CIRCUIT SUBSTRATE AND PACKAGE STRUCTURE
The invention provides a circuit substrate and a package structure. The circuit substrate includes a molding compound having a chip-side surface and a solder...
2016/0172288 INTERPOSER WITH LATTICE CONSTRUCTION AND EMBEDDED CONDUCTIVE METAL STRUCTURES
A lattice structure is formed in a non-silicon interposer substrate to create large cells that are multiples of through hole pitches to act as islands for...
2016/0172287 WIRING BOARD AND SEMICONDUCTOR DEVICE
A wiring board includes a first wiring layer, a first insulating layer, first via wirings, connection terminals and a protection layer. The first insulating...
2016/0172286 SEMICONDUCTOR PACKAGE, MODULE SUBSTRATE AND SEMICONDUCTOR PACKAGE MODULE HAVING THE SAME
Semiconductor packages, module substrates and semiconductor package modules having the same are provided. The semiconductor package module includes a module...
2016/0172285 POWER MODULE
A power module includes a first substrate, at least two power elements, at least one first conductive structure and at least one leadframe. The first substrate...
2016/0172284 Integrated Power Assembly with Stacked Individually Packaged Power Devices
An integrated power assembly is disclosed. The integrated power assembly includes a first leadframe having partially etched segments, a first semiconductor die...
2016/0172283 Power Semiconductor Package Having Reduced Form Factor and Increased Current Carrying Capability
A power semiconductor package is disclosed. The power semiconductor package includes a leadframe having partially etched segments and at least one non-etched...
2016/0172282 POST-MOLD FOR SEMICONDUCTOR PACKAGE HAVING EXPOSED TRACES
Method of and devices for protecting semiconductor packages are provided. The methods and devices comprise loading a leadframe containing multiple ...
2016/0172281 PACKAGING STRUCTURE
A packaging structure includes a lead frame, a chip, and a packaging material. The lead frame has a pair of opposed first surface and second surface, and has a...
2016/0172280 POWER FIELD-EFFECT TRANSISTOR (FET), PRE-DRIVER, CONTROLLER, AND SENSE RESISTOR INTEGRATION FOR MULTI-PHASE...
Techniques are described for integrating power field-effect transistors (FETs), pre-drivers, controllers, and/or resistors into a common multi-chip package for...
2016/0172279 Integrated Power Assembly with Reduced Form Factor and Enhanced Thermal Dissipation
An integrated power assembly is disclosed. The integrated power assembly includes a printed circuit board, a first leadframe having partially etched segments...
2016/0172278 ASSEMBLY OF AN INTEGRATED CIRCUIT CHIP AND OF A PLATE
An assembly is made of an integrated circuit chip and a plate. At least one channel is arranged between the chip and the plate. The channel is delimited by...
2016/0172277 LAND STRUCTURE FOR SEMICONDUCTOR PACKAGE AND METHOD THEREFOR
In one embodiment, a method for forming a package substrate includes selectively removing portions of a lead frame to form cavities and filling the cavities...
2016/0172276 Bonding clip, carrier and method of manufacturing a bonding clip
Various embodiments provide a clip for clip bonding of a die to a carrier (bonding clip), wherein the clip comprises a clip body comprising a first region...
2016/0172275 PACKAGE FOR A SURFACE-MOUNT SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A surface-mount electronic device includes a body of semiconductor material, a lead frame, which forms a plurality of contact terminals, and a package...
2016/0172274 SYSTEM, APPARATUS, AND METHOD FOR SEMICONDUCTOR PACKAGE GROUNDS
A semiconductor package according to some examples may include a first portion of a support plate configured as an RF signal connection, a semiconductor die...
2016/0172273 INTEGRATED CIRCUIT DEVICE WITH PLATING ON LEAD INTERCONNECTION POINT AND METHOD OF FORMING THE DEVICE
An integrated circuit (IC) device includes an IC die and a plurality of leads. Each lead includes an unplated proximal end including a first material, and an...
2016/0172272 INTEGRATED CIRCUIT (IC) PACKAGE WITH A SOLDER RECEIVING AREA AND ASSOCIATED METHODS
A single chip integrated circuit (IC) package includes a die pad, and a spacer ring on the die pad defining a solder receiving area. A solder body is on the...
2016/0172271 Techniques for Interconnecting Stacked Dies Using Connection Sites
An integrated circuit die includes conductive connection sites located at least on a surface of the integrated circuit die within a contiguous region thereof....
2016/0172270 INSULATING SHEET AND MANUFACTURING METHOD FOR SAME
A heat-insulating sheet includes a heat storage sheet, a first insulating sheet, and a thermally conductive sheet. The heat storage sheet contains a first...
2016/0172269 SEMICONDUCTOR PACKAGE
A dummy bump electrode for heat-dissipating is provided on a surface of a semiconductor chip. The semiconductor chip is mounted on a wiring substrate. A lead...
2016/0172268 Bond Via Array for Thermal Conductivity
In a microelectronic device, a substrate has first upper and lower surfaces. An integrated circuit die has second upper and lower surfaces. Interconnects...
2016/0172267 CIRCUIT DEVICE AND METHOD OF MANUFACTURING A CIRCUIT DEVICE FOR CONTROLLING A TRANSMISSION OF A VEHICLE
A circuit device for controlling a transmission of a vehicle comprises an integrated circuit, which is mounted with a first surface on a first support surface...
2016/0172266 SEMICONDUCTOR DEVICE
A semiconductor device includes a transistor, a package in which the transistor is molded, a first heatsink plate, and a second heatsink plate. The first...
2016/0172265 SEMICONDUCTOR PACKAGE
A semiconductor package includes a first semiconductor device provided on a support substrate; a first encapsulation material covering the first semiconductor...
2016/0172264 PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF
A method for fabricating a package structure is provided, including the steps of: disposing and electrically connecting a sensing chip to a substrate; forming...
2016/0172263 METHOD AND STRUCTURE FOR WAFER-LEVEL PACKAGING
A method for wafer-level packaging includes providing a semiconductor wafer having a plurality of semiconductor chips connected by connection stems in the...
2016/0172262 INTEGRATED CIRCUIT DEVICE WITH SHAPED LEADS AND METHOD OF FORMING THE DEVICE
An integrated circuit (IC) device includes an IC and encapsulating material surrounding the IC. Leads are coupled to the IC and extend outwardly from sides of...
2016/0172261 ULTRA FINE PITCH PoP CORELESS PACKAGE
A bottom package for a PoP (package-on-package) may be formed with a reinforcement layer supporting a thin or coreless substrate. The reinforcement layer may...
2016/0172260 ELECTRONIC COMPONENT HOUSING PACKAGE AND ELECTRONIC APPARATUS
An electronic component housing package and the like capable of reducing time of infrared heating operation are provided. An electronic component housing...
2016/0172259 CUSTOMIZED MODULE LID
A method of forming a custom module lid. The method may include placing a multichip module (MCM) between a module base and a temporary lid, target components...
2016/0172258 METHOD OF ENDPOINT DETECTION OF PLASMA ETCHING PROCESS USING MULTIVARIATE ANALYSIS
Described is a method for determining an endpoint of an etch process using optical emission spectroscopy (OES) data as an input. Optical emission spectroscopy...
2016/0172257 ETCHING PROCESSING METHOD AND BEVEL ETCHING APPARATUS
Disclosed is an etching processing method using a bevel etching apparatus for etching a substrate by irradiating a laser beam, the bevel etching apparatus...
2016/0172256 Detection of Lost Wafer from Spinning Chuck
The disclosure relates to systems and methods for detecting when a microelectronic substrate is no longer properly secured or lost from a rotating chuck. A...
2016/0172255 WAFER PROCESSING APPARATUSES AND METHODS OF OPERATING THE SAME
Wafer processing apparatuses and methods of operating the same are provided herein. In an embodiment, a wafer processing apparatus includes a rotatable platen...
2016/0172254 MEASURING DEVICE AND METHOD FOR MEASURING LAYER THICKNESSES AND DEFECTS IN A WAFER STACK
A method for measuring and/or acquiring layer thicknesses and voids of one or more layers of a temporary bonded wafer stack on a plurality of measuring points...
2016/0172253 ELECTRIC-PROGRAMMABLE MAGNETIC MODULE AND PICKING-UP AND PLACEMENT PROCESS FOR ELECTRONIC DEVICES
A picking-up and placement process for electronic devices comprising: (a) providing a first substrate having a plurality of electronic devices formed thereon,...
2016/0172252 ALIGNMENT OF THREE DIMENSIONAL INTEGRATED CIRCUIT COMPONENTS
A method for aligning a chip onto a substrate is disclosed. The method includes, depositing a ferrofluid, onto a substrate that has one or more pads that...
2016/0172251 INTEGRATED CIRCUITS AND METHODS OF FORMING THE SAME WITH EFFECTIVE DUMMY GATE CAP REMOVAL
Integrated circuits and methods of forming the same are provided. An exemplary method of forming an integrated circuit includes forming a dummy gate structure...
2016/0172250 Semiconductor Isolation Structure with Air Gaps in Deep Trenches
A device includes a semiconductor substrate, a contact plug over the semiconductor substrate, and an Inter-Layer Dielectric (ILD) layer over the semiconductor...
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