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Patent # Description
2016/0172249 DESIGN STRUCTURE FOR METAL OXIDE SEMICONDUCTOR CAPACITOR
A design structure for a semiconductor structure is disclosed. The semiconductor structure can include a substrate, a set of semiconductor fins positioned on...
2016/0172248 Method of Forming Semiconductor Device with Different Threshold Voltages
A method for fabricating a semiconductor device includes forming a first gate stack over a first fin feature and second gate stack over a second fin feature,...
2016/0172247 METHOD OF FORMING SEMICONDUCTOR DEVICE WITH DIFFERENT THRESHOLD VOLTAGES
A method for fabricating a semiconductor device includes forming a first gate stack over a first fin feature and second gate stack over a second fin feature,...
2016/0172246 NANOWIRE CMOS STRUCTURE AND FORMATION METHODS
A method includes growing a nanowire from a substrate, forming a sacrificial layer surrounding the nanowire, removing the nanowire from the sacrificial layer...
2016/0172245 Method of forming a Gate Shield in an ED-CMOS Transistor and a base of a bipolar transistor using BICMOS...
A method of fabricating a MOSFET transistor in a SiGe BICMOS technology and resulting structure having a drain-gate feedback capacitance shield formed between...
2016/0172244 METHOD FOR MANUFACTURING ELECTRONIC DEVICE COMPRISING A RESIN SUBSTRATE AND AN ELECTRONIC COMPONENT
An electronic component manufacturing method according to an aspect of the present disclosure includes providing a support substrate, forming a release layer...
2016/0172243 WAFER MATERIAL REMOVAL
One example discloses a system for wafer material removal, including: a wafer structures map, identifying a first device structure having a first location and...
2016/0172242 SEMICONDUCTOR DEVICES AND METHODS FOR BACKSIDE PHOTO ALIGNMENT
Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic...
2016/0172241 ELECTROLESS METAL THROUGH SILICON VIA
A method of making a substrate-through metal via having a high aspect ratio, in a semiconductor substrate, and a metal pattern on the substrate surface,...
2016/0172240 METHOD FOR FORMING A COUPLING LAYER
Molecules of a coupling layer composition in a semiconductor device are bidimensionally polymerized in order to provide enhanced moisture blocking effect,...
2016/0172239 ULTRA-THIN DIELECTRIC DIFFUSION BARRIER AND ETCH STOP LAYER FOR ADVANCED INTERCONNECT APPLICATIONS
Implementations described herein generally relate to the formation of a silicon and aluminum containing layer. Methods described herein can include positioning...
2016/0172238 SELECTIVE SEALANT REMOVAL
A method of forming features in a low-k dielectric layer is described. A via, trench or a dual damascene structure may be present in the low-k dielectric layer...
2016/0172237 NON-LITHOGRAPHICALLY PATTERNED DIRECTED SELF ASSEMBLY ALIGNMENT PROMOTION LAYERS
A method of an aspect includes forming a directed self assembly alignment promotion layer over a surface of a substrate having a first patterned region and a...
2016/0172236 DEVICE SUBSTRATES, INTEGRATED CIRCUITS AND METHODS FOR FABRICATING DEVICE SUBSTRATES AND INTEGRATED CIRCUITS
Integrated circuits and methods for fabricating device substrates and integrated circuits are provided. Integrated circuits in accordance with those described...
2016/0172235 IN-SITU DOPED POLYSILICON FILLER FOR TRENCHES
A method of fabricating an integrated circuit (IC) includes etching a trench in a semiconductor substrate having an aspect ratio (AR) .gtoreq.5 and a trench...
2016/0172234 METHOD OF FORMING A SEMICONDUCTOR DEVICE INCLUDING TRENCH TERMINATION AND TRENCH STRUCTURE THEREFOR
In an embodiment, a method of forming a semiconductor may include forming a plurality of active trenches and forming a termination trench substantially...
2016/0172233 METHOD OF FABRICATING SEMICONDUCTOR DEVICE
A method of fabricating a semiconductor device includes: forming a metal layer containing Al; forming an insulating film on the metal layer; forming an opening...
2016/0172232 Interconnect Having Air Gaps and Polymer Wrapped Conductive Lines
A method includes depositing a first polymer layer over a first dielectric layer, forming a first opening and a second opening using an etching process,...
2016/0172231 METHOD FOR RESIDUE-FREE BLOCK PATTERN TRANSFER ONTO METAL INTERCONNECTS FOR AIR GAP FORMATION
A selective wet etching process is used, prior to air gap opening formation, to remove a sacrificial nitride layer from over a first region of an interconnect...
2016/0172230 DICING TAPE-INTEGRATED FILM FOR SEMICONDUCTOR BACK SURFACE AND METHOD FOR PRODUCING THE FILM, AND METHOD FOR...
The present invention relates to a dicing tape-integrated film for semiconductor back surface, which includes: a dicing tape including a base material having...
2016/0172229 STIFFENER TAPE FOR ELECTRONIC ASSEMBLY
Some example forms relate to a stiffener tape for a wafer. The stiffener tape includes a mounting tape and a stiffener removably attached to the mounting tape....
2016/0172228 Method of laser separation of the epitaxial film or the epitaxial film layer from the growth substrate of the...
The present invention proposes variations of the laser separation method allowing separating homoepitaxial films from the substrates made from the same...
2016/0172227 ELECTROSTATIC CHUCK DESIGN FOR HIGH TEMPERATURE RF APPLICATIONS
An electrostatic chuck includes a puck having a support surface to support a substrate when disposed thereon and an opposing second surface, wherein one or...
2016/0172226 GAS COOLED MINIMAL CONTACT AREA(MCA) ELECTROSTATIC CHUCK(ESC) FOR ALUMINUM NITRIDE(ALN) PVD PROCESS
Embodiments of the disclosure include an electrostatic chuck assembly, a processing chamber and a method of maintaining a temperature of a substrate is...
2016/0172225 SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING SYSTEM, AND METHOD OF DETECTING ABNORMALITY IN TRANSPORT...
A substrate processing apparatus includes: a load port into and out of which the transport container is carried; and an apparatus controller that controls...
2016/0172224 SUBSTRATE TRANSFER UNIT, SUBSTRATE TREATING APPARATUS INCLUDING THE SAME, AND SUBSTRATE TREATING METHOD
A substrate transfer unit includes a rotation body, an arm member, and first and second blades. The arm member is on the rotation body, and the first and...
2016/0172223 GAS PURGE DEVICE AND GAS PURGE METHOD
A gas inlet made of an elastic material is prevented from getting scratched by contact with a nozzle, and adhesion between the gas inlet and the nozzle is...
2016/0172222 METHODS AND DEVICES FOR SECURING AND TRANSPORTING SINGULATED DIE IN HIGH VOLUME MANUFACTURING
A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database,...
2016/0172221 SUBSTRATE PROCESSING APPARATUS
A substrate processing apparatus includes first and second polishing units for polishing a peripheral portion of a substrate, a primary cleaning unit for...
2016/0172220 SELENIZATION PROCESS APPARATUS FOR GLASS SUBSTRATE
A selenization process apparatus for a glass substrate includes a first heating unit disposed in a chamber; a conveying heating module disposed in the chamber...
2016/0172219 TEMPERATURE CONTROL SYSTEM FOR SEMICONDUCTOR MANUFACTURING SYSTEM
Provided is a temperature control system configured to mix a low temperature heating medium and a high temperature heating medium to supply the heating mediums...
2016/0172218 HEAT TREATMENT APPARATUS, HEAT TREATMENT METHOD, AND STORAGE MEDIUM
Disclosed is a heat treatment apparatus for performing a heat treatment on a coating film formed on a substrate. The apparatus includes a placing unit provided...
2016/0172217 PLASMA PROCESSING APPARATUS
A plasma processing apparatus includes: a processing container; a processing gas supply unit; a mounting table configured to mount a to-be-processed substrate...
2016/0172216 Ion Energy Control By RF Pulse Shape
A method for slope control of ion energy is described. The method includes receiving a setting indicating that an etch operation is to be performed using a...
2016/0172215 METHOD FOR REPAIRING SEMICONDUCTOR PROCESSING COMPONENTS
A method of repairing a semiconductor processing component is provided, in which the method includes preparing a semiconductor processing component including a...
2016/0172214 Molded Electronic Package Geometry To Control Warpage And Die Stress
A method and system are provided for a molded electronic package geometry that enables control of warpage and die stress. A mold tool can be closed to define a...
2016/0172213 THERMAL PROCESSING IN SILICON
A method is provided for the processing of a device having a crystalline silicon region containing an internal hydrogen source. The method comprises: i)...
2016/0172212 PLASMA PROCESSING METHOD
A plasma processing method uses a plasma processing apparatus including a processing chamber, a mounting table provided in the processing chamber and...
2016/0172211 UV ASSISTED CVD ALN FILM FOR BEOL ETCH STOP APPLICATION
Implementations described herein generally relate to methods for depositing etch stop layers, such as AlN layers, using UV assisted CVD. Methods disclosed...
2016/0172210 SEMICONDUCTOR MANUFACTURING APPARATUS AND SEMICONDUCTOR MANUFACTURING METHOD
In one embodiment, a semiconductor manufacturing apparatus includes a wafer setting module including an upper face provided with one or more openings, a wafer...
2016/0172209 CMP-FRIENDLY COATINGS FOR PLANAR RECESSING OR REMOVING OF VARIABLE-HEIGHT LAYERS
An IC device manufacturing process effectuates a planar recessing of material that initially varies in height across a substrate. The method includes forming a...
2016/0172208 CHEMICAL MECHANICAL PLANARIZATION TOPOGRAPHY CONTROL VIA IMPLANT
Systems and methods for chemical mechanical planarization topography control via implants are disclosed. In one embodiment, a method of manufacturing a...
2016/0172207 PELLICLE MEMBRANE AND METHOD OF MANUFACTURING THE SAME
A method of manufacturing a pellicle membrane includes forming a silicon layer on a substrate, forming a mask pattern on the silicon layer, and performing a...
2016/0172206 FAST-GAS SWITCHING FOR ETCHING
A method for etching a layer in a plasma chamber with an inner injection zone gas feed and an outer injection zone gas feed is provided. The layer is placed in...
2016/0172205 PLASMA ETCHING METHOD
A plasma etching method can form a hole having a required opening diameter in a silicon nitride layer, while suppressing a tip end portion of the hole from...
2016/0172204 DEVICE OF CHANGING GAS FLOW PATTERN AND A WAFER PROCESSING METHOD AND APPARATUS
The present invention relates to a device of changing the gas flow pattern in the process chamber and a wafer processing method and system; a gas introduced...
2016/0172203 METHOD FOR MANUFACTURING SEMICONDUCTOR CHIP AND METHOD FOR POSITIONING CUTTING MEMBER
Provided is a method for manufacturing a semiconductor chip including forming a groove on a front surface side along a cut area of a substrate, and a concave...
2016/0172202 INTEGRATED CIRCUITS WITH BACKSIDE METALIZATION AND PRODUCTION METHOD THEREOF
An embodiment of an integrated device, including a chip of semiconductor material wherein an integrated circuit is integrated, is proposed; the integrated...
2016/0172201 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
The present invention improves the performance of a semiconductor device. In a manufacturing method of a semiconductor device, sacrificial oxide films are...
2016/0172200 METHOD FOR FABRICATING NON-VOLATILE MEMORY DEVICE
A method for fabricating non-volatile memory device is disclosed. The method includes the steps of: providing a substrate having a stack structure thereon;...
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