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Patent # Description
2016/0182094 RECEIVER FOR CARRIER AGGREGATION
A single hybrid receiver is provided for processing both single carrier and carrier aggregated (CA) communications signals where carriers are split into...
2016/0182093 SOFT DECISION DECODING METHOD AND SYSTEM THEREOF
Method and system for soft decision decoding are provided. A soft decision decoding method implemented by a receiver in a communication network may include:...
2016/0182092 Forward Error Control Coding
A system and method for providing error control coding for backhaul applications are disclosed. Data is first encoded using Reed-Solomon (RS) coding. The...
2016/0182091 IMPROVED ERROR CONTROL CODING AN DECODING FOR SERIAL CONCATENATED CODES
A broadcast TV signal is a DVB-T2 based system. The DVB-T2 transmitter offsets the BCH codeword with respect to the LDPC codeword, such that, e.g., the first...
2016/0182090 INTERLEAVING METHOD AND APPARATUS FOR ADAPTIVELY DETERMINING INTERLEAVING DEPTH
An interleaving method and apparatus for adaptively determining an interleaving depth of each of one or more interleaving blocks based on a maximum...
2016/0182089 REED-SOLOMON ERASURE DECODING WITH ERROR DETECTION FOR RETRANSMISSION
By utilizing Reed-Solomon erasure decoding algorithms and techniques, the system is able to perform error detection for the case where the number of bytes...
2016/0182088 Method For File Updating And Version Control For Linear Erasure Coded And Network Coded Storage
Described herein are systems and processes to provide file updating for distributed storage performed using linear codes, such as network codes and random...
2016/0182087 GLDPC SOFT DECODING WITH HARD DECISION INPUTS
A decoder includes circuitry and a soft decoder. The circuitry is configured to receive channel hard decisions for respective bits of a Generalized Low-Density...
2016/0182086 SYSTEMS AND METHODS FOR SOFT DECISION GENERATION IN A SOLID STATE MEMORY SYSTEM
Systems and method relating generally to solid state memory, and more particularly to systems and methods for generated data from a solid state memory. A data...
2016/0182085 PATH ENCODING AND DECODING
This invention relates to a system, method and computer program product for encoding an input string of binary characters including: a cellular data structure...
2016/0182084 PHYSICAL LAYER ENCODING AND DECODING METHOD AND APPARATUSES THEREOF
This application discloses a physical layer encoding and decoding method and apparatuses thereof, where the method includes: receiving an MII control block and...
2016/0182083 Systems and Methods for Decoder Scheduling With Overlap and/or Switch Limiting
The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for scheduling in a data decoder.
2016/0182082 DELTA-SIGMA MODULATOR AND PROGRAM OF DELTA-SIGMA MODULATOR
There is provided a .DELTA..SIGMA. modulator including a loop filter for inputting an m-value digital signal into a subtractor, an n-value quantizer for...
2016/0182081 CAPACITANCE-TO-DIGITAL CONVERTER UTILIZING DIGITAL FEEDBACK AND AUXILIARY DAC
A capacitance-to-digital converter circuit s a capacitor bridge circuit to sense a difference in capacitance between sense capacitors and fixed capacitors in...
2016/0182080 HIGH-SPEED, LOW-POWER RECONFIGURABLE VOLTAGE-MODE DAC-DRIVER
A low-power reconfigurable voltage-mode digital-to-analog converter (DAC) driver circuit includes a first and a second supply voltage and a number of DAC...
2016/0182079 DAC WITH SUB-DACS AND RELATED METHODS
A DAC may include a decoder configured to receive a digital input signal, and first and second sub-DACs coupled in parallel to the decoder, each of the first...
2016/0182078 SAR ADCS WITH DEDICATED REFERENCE CAPACITOR FOR EACH BIT CAPACITOR
A successive approximation register analog-to-digital converter (SAR ADC) typically includes circuitry for implementing bit trials that converts an analog...
2016/0182077 CALIBRATION TECHNIQUES FOR SAR ADCS WITH ON-CHIP RESERVOIR CAPACITORS
When reservoir capacitors are moved on-chip for individual bit decisions, a successive approximation register analog-to-digital converter (SAR ADC) has an...
2016/0182076 Background Calibration for Digital-to-Analog Converters
A system and method where a comparator is operatively coupled to an output of a Digital-to-analog Converter (DAC). The DAC may comprise a single DAC core or a...
2016/0182075 RANDOMLY SAMPLING REFERENCE ADC FOR CALIBRATION
Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to...
2016/0182074 MICROPROCESSOR-ASSISTED CALIBRATION FOR ANALOG-TO-DIGITAL CONVERTER
Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to...
2016/0182073 EFFICIENT CALIBRATION OF ERRORS IN MULTI-STAGE ANALOG-TO-DIGITAL CONVERTER
Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to...
2016/0182072 NOISE-SHAPING CIRCUIT, DIGITAL-TO-TIME CONVERTER, ANALOG-TO-DIGITAL CONVERTER, DIGITAL-TO-ANALOG CONVERTER...
A noise shaping circuit according to an example includes a forward signal path configured to generate an output signal based on an input signal, a feedback...
2016/0182071 METHOD AND DEVICE FOR ANALOG-TO-DIGITAL CONVERSION OF SIGNALS, CORRESPONDING APPARATUS
One or more first signals and one or more second signals, wherein the second signal(s) are slowly varying or low frequency signals in comparison with the first...
2016/0182070 ANALOG-TO-DIGITAL CONVERTER AND ANALOG-TO-DIGITAL CONVERSION METHOD
An analog-to-digital converter may include a voltage-controlled oscillator suitable for generating an oscillation wave with a frequency corresponding to an...
2016/0182069 ATOMIC RESONANCE TRANSITION DEVICE, ATOMIC OSCILLATOR, TIMEPIECE, ELECTRONIC APPARATUS AND MOVING OBJECT
An atomic resonance transition device includes an atomic cell in which an atom is sealed, a first light source part to emit a first light resonant with a D1...
2016/0182068 INJECTION LOCKED DIGITAL FREQUENCY SYNTHESIZER CIRCUIT
The present invention relates to a technique capable of implementing a frequency synthesizer circuit separated into a frequency synthesizer circuit part and an...
2016/0182067 All-Digital-Phase-Locked-Loop Having a Time-to-Digital Converter Circuit with a Dynamically Adjustable Offset Delay
An all-digital-phase-locked-loop (ADPLL) includes a digitally controlled oscillator (DCO) arranged to generate a DCO output signal, and a feedback loop...
2016/0182066 AUTO FREQUENCY CONTROL CIRCUIT AND RECEIVER
According to an embodiment, an auto frequency control circuit includes a peak time detector, a first time shifter a zero-crossing time detector, and a second...
2016/0182065 COARSE TUNING SELECTION FOR PHASE LOCKED LOOPS
A phase locked loop system comprises a phase locked loop and an oscillator that is coarse tuned and fine tuned according to coarse tuning operations and fine...
2016/0182064 CHARGE PUMP CIRCUIT, PHASE LOCKED LOOP APPARATUS, INTEGRATED CIRCUIT, AND METHOD OF MANUFACTURE OF A CHARGE PUMP
A charge pump circuit comprises a first bipolar transistor device and a second bipolar switching device arranged in a differential pair configuration. A first...
2016/0182063 DELAY LOCKED LOOP CIRCUIT
A delay locked loop (DLL) circuit may include: a DLL unit suitable for generating an internal clock by delaying an external clock by a delay amount required...
2016/0182062 READOUT SYSTEM
A readout system includes a sensing module to generate first and second voltage signals with a phase difference associated with an environmental parameter, and...
2016/0182061 DIGITAL PHASE CONTROLLED DELAY CIRCUIT
An adjustable phase clock generator circuit is described that may include a DLL and a phase adjustor to further adjust the phase of a selected clock phase from...
2016/0182060 DUTY CYCLE DETECTION CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME
A duty cycle detection circuit may include a detection block configured to generate a duty detection signal by detecting a duty cycle of an input clock; and a...
2016/0182059 Phase Switching PLL and Calibration Method
The phase-locked loop (PLL) presented herein controls the phase of the output of the PLL. To that end, the PLL includes an oscillator that generates an output...
2016/0182058 METHOD FOR CLOCK CALIBRATION
A system may include a plurality of devices, wherein each device of the plurality of devices has a respective clock source. A first device of the plurality of...
2016/0182057 SLOW-CLOCK CALIBRATION METHOD AND UNIT, CLOCK CIRCUIT, AND MOBILE COMMUNICATION TERMINAL
A slow-clock calibration method, a slow-clock calibration unit, a clock circuit and a mobile communication terminal are provided. The calibration method...
2016/0182056 SYSTEM AND METHOD FOR PROVIDING PROGRAMMABLE SYNCHRONOUS OUTPUT DELAY IN A CLOCK GENERATION OR DISTRIBUTION DEVICE
A clock frequency division circuit receives delay value, synchronization signal, and external clock signal of a given frequency. The clock division circuit...
2016/0182055 DEVICES FOR UTILIZING SYMFETS FOR LOW-POWER INFORMATION PROCESSING
A Boolean gate includes at least one symmetric tunneling field-effect transistor (SymFET) for low-power information processing. SymFETs are ideal for...
2016/0182054 Configurable Logic Circuit Including Dynamic Lookup Table
In some embodiments, a circuit may include a configurable logic module including a multiplexer. The multiplexer may include a plurality of data inputs...
2016/0182053 LEVEL-SHIFTING LATCH
A level-shifting latch circuit for coupling a first circuit in a first voltage domain with a second circuit in a second voltage domain, includes an input node...
2016/0182052 LEVEL-SHIFTING LATCH
A level-shifting latch circuit for coupling a first circuit in a first voltage domain with a second circuit in a second voltage domain, includes an input node...
2016/0182051 Level-Shifter Circuit for Low-Input Voltages
In some embodiments, a method may include receiving an input signal at an input stage of a circuit and amplifying the input signal using an amplifier of the...
2016/0182050 CIRCUIT TECHNIQUE TO ENHANCE SLEW RATE FOR HIGH SPEED APPLICATIONS
A circuit is disclosed. The circuit includes an output driver with a pull-up device, and a pull-down device. The circuit also includes a pre-driver, configured...
2016/0182049 Push-Pull Driver, A Transmitter, A Receiver, A Transceiver, An Integrated Circuit, A Method for Generating a...
A push-pull driver according to an example includes a push stage coupled via a first coupling capacitor to an output of the push-pull driver and a pull stage...
2016/0182048 LEVEL SHIFTER AND DISPLAY DEVICE INCLUDING THE SAME
A level shifter may include: a phase controller configured to determine the number of phases of a gate pulse, using an on input signal and an off input signal,...
2016/0182047 METHOD FOR COMMUNICATION ACROSS VOLTAGE DOMAINS
A system may include a plurality of units, wherein each unit has a respective common mode voltage terminal, communication up terminal, and communication down...
2016/0182046 CROSSTALK COMPENSATION CIRCUIT
Embodiments include apparatuses, methods, and systems for crosstalk compensation. In embodiments, a transmitter may include a crosstalk compensation circuit...
2016/0182045 RELIABILITY OF PHYSICAL UNCLONABLE FUNCTION CIRCUITS
Techniques and circuits are disclosed for obtaining a physical unclonable function (PUF) circuit that is configured to provide, during a first operational...
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