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Patent # Description
2016/0181294 BACKSIDE ILLUMINATED IMAGE SENSOR AND MANUFACTURING METHOD THEREFOR
The present invention relates to a backside illuminated image sensor and a manufacturing method therefor. The backside illuminated image sensor comprises: a...
2016/0181293 Semiconductor Photomultiplier
The present disclosure relates to a semiconductor photomultiplier comprising a substrate; an array of photosensitive cells formed on the substrate that are...
2016/0181292 THIN-FILM TRANSISTOR, METHOD OF MANUFACTURING THE SAME, AND METHOD OF MANUFACTURING BACKPLANE FOR FLAT PANEL...
Provided are a thin-film transistor (TFT), a method of manufacturing the same, and a method of manufacturing a backplane for a flat panel display (FPD). The...
2016/0181291 SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device (100A) includes a first metal layer (12) including a gate electrode (12g); a gate insulating layer (14) formed on the first metal layer;...
2016/0181290 THIN FILM TRANSISTOR AND FABRICATING METHOD THEREOF, AND DISPLAY DEVICE
A thin film transistor and a fabricating method thereof, and a display device are disclosed according to embodiments of the present invention, which...
2016/0181289 ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY DEVICE, THIN FILM TRANSISTOR AND MANUFACTURING METHOD...
An array substrate and manufacturing method thereof, a display device, a thin film transistor and manufacturing method thereof are provided. The manufacturing...
2016/0181288 DEFORMABLE ELECTRONIC DEVICE AND METHODS OF PROVIDING AND USING DEFORMABLE ELECTRONIC DEVICE
Some embodiments include a method of providing an electronic device. The method includes: (i) providing a carrier substrate, (ii) providing a device substrate...
2016/0181287 FLEXIBLE SUBSTRATE, MANUFACTURING METHOD THEREOF AND FLEXIBLE DISPLAY DEVICE
A flexible substrate, a manufacturing method thereof and a flexible display device are disclosed. The flexible substrate includes a display panel region and a...
2016/0181286 FFS ARRAY SUBSTRATE AND LIQUID CRYSTAL DISPLAY DEVICE HAVING THE SAME
An FFS array substrate and a liquid crystal display device having the same are disclosed. The FFS array substrate includes a substrate, first metal layer, a...
2016/0181285 UNIFORM JUNCTION FORMATION IN FINFETS
The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming an abrupt junction in the channel...
2016/0181284 THIN FILM TRANSISTOR ARRAY PANEL AND METHOD OF MANUFACTURING THE PANEL
A thin film transistor array panel includes: a gate line disposed on a substrate and including a first connection member of a gate driver region and a gate...
2016/0181283 THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD OF THE SAME
A thin film transistor ("TFT") array panel includes; an insulation substrate, a TFT disposed on the insulation substrate and including a drain electrode, a...
2016/0181282 DISPLAY DEVICE
A display device includes a display unit including a plurality of pixels respectively including thin film transistors; and a terminal unit including an array...
2016/0181281 DISPLAY PANEL HAVING IMPROVED BRIGHTNESS AND METHOD FOR FABRICATING THE SAME
A display panel comprises a substrate, a gate line, a data line insulated from the gate line, a thin film transistor electrically connected to the gate line...
2016/0181280 ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY PANEL
The disclosure relates to an array substrate and a manufacturing method thereof, and a display panel. The array substrate includes a plurality of data lines...
2016/0181279 ARRAY SUBSTRATE FOR DISPLAY DEVICES
An array substrate for display devices is provided. According to an exemplary embodiment, the array substrate for display device includes: a plurality of gate...
2016/0181278 ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE
The present disclosure relates to the field of liquid crystal display technology, and provides an array substrate, its manufacturing method and a display...
2016/0181277 Multiple VT in III-V FETS
In one aspect, a method of forming a multiple V.sub.T device structure includes the steps of: forming an alternating series of channel and barrier layers as a...
2016/0181276 MULTI-ORIENTATION SOI SUBSTRATES FOR CO-INTEGRATION OF DIFFERENT CONDUCTIVITY TYPE SEMICONDUCTOR DEVICES
A method of forming a semiconductor device that includes providing a base semiconductor substrate having a first orientation crystal plane, and forming an...
2016/0181275 NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
A nonvolatile memory device includes a substrate comprising a first word line formation area, a second word line formation area, and a support area interposed...
2016/0181274 SEMICONDUCTOR MEMORY DEVICE
A method of manufacturing a semiconductor device includes forming a laminated structure including sacrificial layers and a select gate layer on a substrate,...
2016/0181273 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
Disclosed are a semiconductor device and a manufacturing method thereof. According to the semiconductor device and the manufacturing method thereof according...
2016/0181272 Fabricating 3D NAND Memory Having Monolithic Crystalline Silicon Vertical NAND Channel
Disclosed herein are techniques for fabricating 3D NAND memory devices having a mono-crystalline silicon semiconductor vertical NAND channel. Memory holes are...
2016/0181271 METHODS OF FABRICATING MEMORY DEVICE WITH SPACED-APART SEMICONDUCTOR CHARGE STORAGE REGIONS
Methods of fabricating semiconductor devices, such as monolithic three-dimensional NAND memory string devices, include selectively forming semiconductor...
2016/0181270 MEMORY ARCHITECTURE OF ARRAY WITH SINGLE GATE MEMORY DEVICES
A vertical gate nonvolatile NAND array includes a plurality of vertically stacked NAND strings of nonvolatile memory cells, a plurality of word lines arranged...
2016/0181269 THREE DIMENSIONAL STACKED SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
A 3D stacked semiconductor structure is provided, comprising a plurality of stacks vertically formed on a substrate and disposed parallel to each other, a...
2016/0181268 BOUNDARY SCHEME FOR EMBEDDED POLY-SiON CMOS OR NVM IN HKMG CMOS TECHNOLOGY
The present disclosure relates to a structure and method for reducing CMP dishing in integrated circuits. In some embodiments, the structure has a ...
2016/0181267 NON-VOLATILE MEMORY CELL, NAND-TYPE NON-VOLATILE MEMORY, AND METHOD OF MANUFACTURING THE SAME
A non-volatile memory cell, a NAND-type non-volatile memory, and a method of manufacturing the same are provided. The method of manufacturing the non-volatile...
2016/0181266 METHOD FOR FORMING A SPLIT-GATE FLASH MEMORY CELL DEVICE WITH A LOW POWER LOGIC DEVICE
An embedded flash memory device is provided. A gate stack includes a control gate arranged over a floating gate. An erase gate is arranged adjacent to a first...
2016/0181265 MEMORY CELL HAVING A VERTICAL SELECTION GATE FORMED IN AN FDSOI SUBSTRATE
A memory cell formed in a semiconductor substrate, includes a selection gate extending vertically in a trench made in the substrate, and isolated from the...
2016/0181264 THREE DIMENSIONAL NAND MEMORY HAVING IMPROVED CONNECTION BETWEEN SOURCE LINE AND IN-HOLE CHANNEL MATERIAL AS...
A fabrication process is provided for a 3D stacked non-volatile memory device which provides a source contact to a bottom of a memory hole in a stack without...
2016/0181263 NON-VOLATILE PUSH-PULL NON-VOLATILE MEMORY CELL HAVING REDUCED OPERATION DISTURB AND PROCESS FOR MANUFACTURING SAME
A non-volatile memory cell includes a p-channel non-volatile transistor having a source and a drain defining a channel and a gate overlying the channel and an...
2016/0181262 NON-VOLATILE PUSH-PULL NON-VOLATILE MEMORY CELL HAVING REDUCED OPERATION DISTURB AND PROCESS FOR MANUFACTURING SAME
A non-volatile memory cell includes a p-channel non-volatile transistor having a source and a drain defining a channel and a gate overlying the channel and an...
2016/0181261 METHOD TO PREVENT OXIDE DAMAGE AND RESIDUE CONTAMINATION FOR MEMORY DEVICE
The present disclosure relates a method of forming an integrated circuit. In some embodiments, the method is performed by patterning a first masking layer over...
2016/0181260 FUSE CELL CIRCUIT, FUSE CELL ARRAY AND MEMORY DEVICE INCLUDING THE SAME
A fuse cell circuit may include a bit line, a first fuse transistor having first and second program states, a first select transistor coupled between one...
2016/0181259 Vertical ferroelectric memory device and a method for manufacturing thereof
The disclosed technology generally relates to semiconductor devices, and more particularly to a ferroelectric memory device and a method of manufacturing and...
2016/0181258 Methods of Fabricating Semiconductor Devices
Methods of fabricating semiconductor devices include forming a first impurity region in a substrate by implanting a first impurity of a first conductivity type...
2016/0181257 STACKED METAL LAYERS WITH DIFFERENT THICKNESSES
A semiconductor chip includes a plurality of stacked conductive layers. The plurality of stacked conductive layers includes a first conductive layer, a second...
2016/0181256 LOW-DRIVE CURRENT FINFET STRUCTURE FOR IMPROVING CIRCUIT DENSITY OF RATIOED LOGIC IN SRAM DEVICES
A method of fabricating an SRAM semiconductor device includes forming first and second FinFETs on an upper surface of a bulk substrate. The first FinFET...
2016/0181255 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
In an image information chip or the like, a multi-port SRAM is embedded with a logic circuit. When the 3 port is used, the 1 port may serve as a differential...
2016/0181254 LOW-DRIVE CURRENT FINFET STRUCTURE FOR IMPROVING CIRCUIT DENSITY OF RATIOED LOGIC IN SRAM DEVICES
A method of fabricating an SRAM semiconductor device includes forming first and second FinFETs on an upper surface of a bulk substrate. The first FinFET...
2016/0181253 SEMICONDUCTOR STRUCTURES WITH DEEP TRENCH CAPACITOR AND METHODS OF MANUFACTURE
An integrated FinFET and deep trench capacitor structure and methods of manufacture are provided. The method includes forming deep trench capacitor structures...
2016/0181252 DEEP TRENCH POLYSILICON FIN FIRST
After forming a recessed conductive material portion over a deep trench capacitor located in a lower portion of a deep trench embedded in a substrate, a hard...
2016/0181251 SEMICONDUCTOR DEVICE
A semiconductor device includes a first memory cell including a first transistor and a first capacitor, the first transistor comprising a first gate electrode,...
2016/0181250 FINFET BASED ZRAM WITH CONVEX CHANNEL REGION
Embodiments of the present invention provide improved methods and structures for fabrication of capacitor-less DRAM devices, sometimes referred to as ZRAM...
2016/0181249 SEMICONDUCTOR STRUCTURES WITH DEEP TRENCH CAPACITOR AND METHODS OF MANUFACTURE
An integrated FinFET and deep trench capacitor structure and methods of manufacture are provided. The method includes forming a plurality of fin structures...
2016/0181248 CMOS TRANSISTORS INCLUDING GATE SPACERS OF THE SAME THICKNESS
A dielectric material layer is deposited on gate structures of first and second semiconductor material portions. The dielectric material layer is ...
2016/0181247 FIELD-ISOLATED BULK FINFET
Disclosed are isolation techniques for bulk FinFETs. A semiconductor device includes a semiconductor substrate with a fin structure on the semiconductor...
2016/0181246 METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a...
2016/0181245 Short Channel Effect Suppression
A semiconductor device includes a semiconductor substrate having a first region and a second region. The first region includes a first set of fin structures,...
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