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Patent # Description
2016/0181244 SHORT CHANNEL EFFECT SUPPRESSION
A method of fabricating a semiconductor device includes forming a plurality of isolation features on a semiconductor substrate, thereby defining a first set of...
2016/0181243 METHODS OF FABRICATING SEMICONDUCTOR DEVICES INCLUDING FIN-SHAPED ACTIVE REGIONS
A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a...
2016/0181242 PASSIVE DEVICE AND MANUFACTURING METHOD THEREOF
The present invention relates to a passive device and manufacturing method thereof. A capacitor according to the present invention includes: a capacitor thin...
2016/0181241 METHODS OF FORMING TUNEABLE TEMPERATURE COEFFICIENT FR EMBEDDED RESISTORS
Methods of forming resistor structures with tunable temperature coefficient of resistance are described. Those methods and structures may include forming an...
2016/0181240 Semiconductor Device and Method
In an embodiment, a semiconductor device includes a silicon carbide layer comprising a lateral diode, and a Group III nitride based semiconductor device...
2016/0181239 MULTI-LAYERED INTEGRATED CIRCUIT WITH SELECTIVE TEMPERATURE COEFFICIENT OF RESISTANCE
The integrated circuit described herein includes: a first resistor having a first trench in a dielectric layer, the first trench having a first width; a second...
2016/0181238 ELECTROSTATIC PROTECTIVE DEVICE
The present invention discloses an electrostatic protective device structure, which comprises a CMOS transistor that is disposed entirely above a P-type...
2016/0181237 Electrostatic Discharge Protection Structure And Fabrication Method Thereof
An electrostatic discharge protection structure includes: substrate of a first type of conductivity, well region of a second type of conductivity, substrate...
2016/0181236 TRANSIENT VOLTAGE SUPPRESSOR AND ESD PROTECTION DEVICE AND ARRAY THEREOF
Provided is a transient voltage suppressor including a substrate, a well region of a first conductivity type, a first doped region of a second conductivity...
2016/0181235 INTEGRATED CIRCUIT HAVING SPARE CIRCUIT CELLS
Aspects of the disclosure include an integrated circuit that includes a plurality of functional circuit cells and a plurality of inactive spare functional...
2016/0181234 ELECTRONIC DEVICES AND METHODS HAVING A COMPACT MULTI-WAY TRANSFORMER COMBINER
Apparatus having structures implementing compact and symmetric multi-way transformer combiners are described herein. In an embodiment, each unit device cell of...
2016/0181233 METAL-INSULATOR-METAL (MIM) CAPACITORS ARRANGED IN A PATTERN TO REDUCE INDUCTANCE, AND RELATED METHODS
Metal-insulator-metal (MIM) capacitors arranged in a pattern to reduce inductance, and related methods, are disclosed. In one aspect, circuits are provided...
2016/0181232 SEMICONDUCTOR MODULE AND SEMICONDUCTOR DEVICE
A semiconductor module includes first and second semiconductor elements connected in series, an insulating substrate, first and second metal patterns formed on...
2016/0181231 SOLUTION FOR REDUCING POOR CONTACT IN INFO PACKAGES
A package includes a first package including a device die, a molding compound molding the device die therein, a through-via penetrating through the molding...
2016/0181230 ARRAY SUBSTRATE OF ORGANIC LIGHT-EMITTING DIODES AND METHOD FOR PACKAGING THE SAME
An array substrate of organic light-emitting diodes and a method for fabricating the same are provided to narrow an edge frame of product device of organic...
2016/0181229 MOUNTING STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor-device mounting structure includes a first semiconductor device and a plate-shaped second semiconductor device connected to the first...
2016/0181228 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
A semiconductor device includes a first laminated body and a second laminated body. The first laminated body includes sequentially a first element, a first...
2016/0181227 NON-CONTACTING INDUCTIVE INTERCONNECTS
A non-contacting inductive interconnect of a three-dimensional integrated circuit includes a first silicon substrate having a first inductive loop. A first...
2016/0181226 STACKED SEMICONDUCTOR CHIP RGBZ SENSOR
An apparatus is described that includes a first semiconductor chip having a first pixel array. The first pixel array has visible light sensitive pixels. The...
2016/0181225 CORROSION-RESISTANT COPPER BONDS TO ALUMINUM
A method for fabricating a semiconductor device is disclosed. A packaged semiconductor device is provided having copper ball bonds attached to aluminum pads....
2016/0181224 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device that includes: preparing a pair of substrates that respectively include a device structure on one primary...
2016/0181223 BUMP STRUCTURE HAVING A SIDE RECESS AND SEMICONDUCTOR STRUCTURE INCLUDING THE SAME
In some embodiments, the present invention relates to a method of integrated chip bonding. The method forms a conductive trace on a surface of a first work...
2016/0181222 PICKHEAD FOR SOLDER BALL PLACEMENT ON AN INTEGRATED CIRCUIT PACKAGE
Embodiments of the present disclosure are directed toward a pickhead for solder ball placement on an integrated circuit (IC) package, and associated systems...
2016/0181221 Semiconductor Module
To provide a semiconductor module that has high reliability of electric connection by a solder and is inexpensive. A joint surface of an electrode jointing...
2016/0181220 Dummy Flip Chip Bumps for Reducing Stress
A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is...
2016/0181219 Solder Joint Structure for Ball Grid Array in Wafer Level Package
A semiconductor device package and a method for forming the same using an improved solder joint structure are disclosure. The package includes solder joints...
2016/0181218 LOW COST PACKAGE WARPAGE SOLUTION
Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may...
2016/0181217 FORMATION OF SOLDER AND COPPER INTERCONNECT STRUCTURES AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS
Embodiments of the present disclosure are directed toward formation of solder and copper interconnect structures and associated techniques and configurations....
2016/0181216 REDUCING SOLDER PAD TOPOLOGY DIFFERENCES BY PLANARIZATION
A technique is disclosed for causing the top surfaces of solder bumps on a chip to be in the same plane to ensure a more reliable bond between the chip and a...
2016/0181215 Three-Dimensional Integrated Circuit Integration
Wiring structures, methods for providing a wiring structure, and methods for distributing currents with a wiring structure from one or more through-substrate...
2016/0181214 STACKED MEMORY CHIP HAVING REDUCED INPUT-OUTPUT LOAD, MEMORY MODULE AND MEMORY SYSTEM INCLUDING THE SAME
A stacked memory chip includes a chip input-output pad unit, a first semiconductor die and a second semiconductor die. The chip input-output pad unit includes...
2016/0181213 WAFER STRUCTURE AND METHOD FOR WAFER DICING
The semiconductor die includes a base body, protruding portions and bonding pads. The base body has sidewalls. The protruding portions are laterally protruding...
2016/0181212 CHIP PACKAGE AND METHOD FOR FORMING THE SAME
A chip package is provided. The chip package includes a substrate having a first surface and a second surface opposite thereto. A dielectric layer is disposed...
2016/0181211 DIE PACKAGE WITH SUPERPOSER SUBSTRATE FOR PASSIVE COMPONENTS
A die package is described that includes a substrate to carry passive components. In one example, the package has a semiconductor die having active circuitry...
2016/0181210 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
An inventive semiconductor device includes a semiconductor chip having a passivation film, and a sealing resin layer provided over the passivation film for...
2016/0181209 Integrated Circuit Having Stress Tuning Layer and Methods of Manufacturing Same
Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of...
2016/0181208 DISCONTINUOUS AIR GAP CRACK STOP
An method including forming multiple interconnect levels on top of one another, each level comprising a metal interconnect and a crack stop both embedded in a...
2016/0181207 METHOD OF MAKING AN ELECTROMAGNETIC INTERFERENCE SHIELD FOR SEMICONDUCTOR CHIP PACKAGES
An electromagnetic interference shield is described for semiconductor chip packages. In some embodiments, a mold compound is formed over a semiconductor die,...
2016/0181206 SEMICONDUCTOR PACKAGE HAVING A METAL PAINT LAYER
Disclosed are devices and methods related to a conductive paint layer configured to provide radio-frequency (RF) shielding for a packaged semiconductor module....
2016/0181205 DISCRETE COMPONENT BACKWARD TRACEABILITY AND SEMICONDUCTOR DEVICE FORWARD TRACEABILITY
A system is disclosed for providing backward and forward traceability by a methodology which identifies discrete components (die, substrate and/or passives)...
2016/0181204 ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME
This patent document provides an electronic device including a semiconductor memory that can simplify a fabrication process and improve characteristics of a...
2016/0181203 ELECTRIC CONTACT STRUCTURE HAVING A DIFFUSION BARRIER FOR AN ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE...
An electric contact structure includes a first structural layer; a second structural layer made of dielectric material extending over the first structural...
2016/0181202 MICROELECTRONIC DEVICES WITH MULTI-LAYER PACKAGE SURFACE CONDUCTORS AND METHODS OF THEIR FABRICATION
An embodiment of a device includes a package body having a first sidewall, a top surface, and a bottom surface, and multiple pads that are exposed at the first...
2016/0181201 SEMICONDUCTOR PACKAGE ASSEMBLY WITH THROUGH SILICON VIA INTERCONNECT
The invention provides a semiconductor package assembly with a TSV interconnect. The semiconductor package assembly includes a first semiconductor die mounted...
2016/0181200 SUBTRACTIVE ETCH INTERCONNECTS
A method of forming an integrated metal line and interconnect. The method may include forming a first trench in a first ILD exposing a lower metal line, the...
2016/0181199 SEMICONDUCTOR DEVICE
According to one embodiment, an integrated circuit is formed on a semiconductor chip, a regulator supplies power to the integrated circuit via the power-supply...
2016/0181198 SEMICONDUCTOR DEVICES HAVING EXPANDED RECESS FOR BIT LINE CONTACT
A semiconductor device includes a first device isolation region and a second device isolation region defining a first active region, a second active region,...
2016/0181197 RELIABLE PASSIVATION LAYERS FOR SEMICONDUCTOR DEVICES
Device and method for forming a device are disclosed. A substrate which is prepared with a dielectric layer having a top metal level of the device is provided....
2016/0181196 PRESERVATION OF FINE PITCH REDISTRIBUTION LINES
An embodiment includes a semiconductor apparatus comprising: a redistribution layer (RDL) including a patterned RDL line having two RDL sidewalls, the RDL...
2016/0181195 SUBSTRATE STRIP AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE USING THE SAME
A substrate includes a substrate body including a plurality of chip mounting regions and a peripheral region surrounding the plurality of chip mounting...
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