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Patent # Description
2016/0181194 SEMICONDUCTOR DEVICE
The present invention is to provide a semiconductor device in which the generation of the eddy current in a metal flat plate is reduced, and the Q value of the...
2016/0181193 PACKAGE STUCTURE AND METHOD OF FABRICATING THE SAME
A package structure and a method of fabricating the same are provided. The method includes forming a first wiring layer on a carrier board, forming a plurality...
2016/0181192 HIGH-TEMPERATURE CYCLING BGA PACKAGING
An example method for attaching a ball grid array chip to a circuit board includes providing an adapter for attaching a chip with a plurality of solder balls...
2016/0181191 SUBSTRATE CORE VIA STRUCTURE
By now it should be appreciated that there has been provided methods for making a packaged semiconductor device (and the resultant device) including a via...
2016/0181190 SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME
A semiconductor device includes a first electronic component mounted to an upper face of a plated interconnect layer, a second electronic component mounted to...
2016/0181189 GROUND VIA CLUSTERING FOR CROSSTALK MITIGATION
Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated...
2016/0181188 AMELIORATED COMPOUND CARRIER BOARD STRUCTURE OF FLIP-CHIP CHIP-SCALE PACKAGE
An ameliorated compound carrier board structure of Flip-Chip Chip-Scale Package has the insulating layer between the carrier board and the substrate in the...
2016/0181187 SEMICONDUCTOR DEVICE AND LEAD FRAME
A semiconductor device includes a lead frame having terminals, a semiconductor chip electrically coupled to the terminals, and a resin part configured to...
2016/0181186 SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR
A semiconductor device includes a semiconductor chip, a lead arranged on a side portion of the semiconductor chip, and a wire, whose one end and another end...
2016/0181185 SEMICONDUCTOR PACKAGE STRUCTURE
A semiconductor package structure includes a lead frame, a chip and a molding compound. The lead frame includes a tray pad and a plurality of leads. Two of the...
2016/0181184 SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
The present invention makes it possible to improve the reliability of a semiconductor device. The semiconductor device has, over a semiconductor substrate, a...
2016/0181183 METHOD FOR PREVENTING DIE PAD DELAMINATION
The invention is directed to a method for inhibiting or preventing delamination at the interface of the die attach/mold compound and the die pad of a...
2016/0181182 ELECTRONIC DEVICE AND METHODS OF PROVIDING AND USING ELECTRONIC DEVICE
Some embodiments include a method of providing an electronic device. The method can comprise: providing a first device substrate; providing one or more first...
2016/0181181 PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING SAME
A method for manufacturing a package structure carries out in following way. A flexible circuit board is provided. The flexible circuit board defines a bent...
2016/0181180 PACKAGED SEMICONDUCTOR DEVICE HAVING ATTACHED CHIPS OVERHANGING THE ASSEMBLY PAD
A semiconductor device (200) comprising a semiconductor chip (201) has an electrically active side (201a) and an opposite electrically inactive side (201b);...
2016/0181179 Through-Substrate Vias with Improved Connections
A device includes a substrate, and a plurality of dielectric layers over the substrate. A plurality of metallization layers is formed in the plurality of...
2016/0181178 Cooling Device for a Current Converter Module
In order to prevent the formation of condensation in a cooling device for a current converter module, the cooling device has a cooling liquid channel, which...
2016/0181177 Cooling Device for a Current Converter Module
In order to keep the temperature difference on the heat exchanger in a cooling device for a current converter module as low as possible, a cooling device has a...
2016/0181176 SEMICONDUCTOR PACKAGE
The present disclosure relates to a semiconductor package. In an embodiment, the semiconductor package includes a substrate, a semiconductor device, a thermal...
2016/0181175 ELECTRONIC MODULE AND METHOD OF MANUFACTURING THE SAME
An electronic module 1 includes an electronic module 10 that includes a substrate 11 and an electronic element 12, an electronic module 20 that includes a...
2016/0181174 INTEGRATED CIRCUIT COOLING APPARATUS
A chip fabricated from a semiconductor material is disclosed, which may include active devices located below a first depth from the chip back side, and a...
2016/0181173 INTEGRATED CIRCUIT BARRIERLESS MICROFLUIDIC CHANNEL
A structure and method for fabricating a continuous cooling channel in the back end of line wiring levels of an integrated circuit (IC) chip is provided. This...
2016/0181172 COMPOSITIONS AND METHODS FOR SEMICONDUCTOR PROCESSING AND DEVICES FORMED THEREFROM
The present invention relates generally to the field of semiconductor devices, including solar cells, and compositions and methods for processing semiconductor...
2016/0181171 Integrated circuit with printed bond connections
A packaged integrated circuit is provided. The packaged integrated circuit includes a die, a package including a base, a lid, and a plurality of package leads,...
2016/0181170 CRIMPING POWER MODULE
A crimping power module includes a shell (10), a cover (12), and an electric insulation substrate (13) crimped to a heat dissipation device. The cover and the...
2016/0181169 ORGANIC-INORGANIC HYBRID STRUCTURE FOR INTEGRATED CIRCUIT PACKAGES
An organic-inorganic hybrid structure is described for integrated circuit packages. In one example, an integrated circuit package includes a ceramic frame...
2016/0181168 Environmental hardened packaged integrated circuit
A packaged integrated circuit for operating reliably at elevated temperatures is provided. The packaged integrated circuit includes a modified extracted die,...
2016/0181167 APPARATUS FOR FORMING A THIN LAYER AND METHOD OF FORMING A THIN LAYER ON A SUBSTRATE USNIG THE SAME
An apparatus and method of forming an epitaxial layer are provided. The apparatus includes a process chamber in which an epitaxial process is performed to form...
2016/0181166 METHOD OF FINE-TUNING PROCESS CONTROLS DURING INTEGRATED CIRCUIT CHIP MANUFACTURING BASED ON SUBSTRATE BACKSIDE...
Disclosed is a method of manufacturing integrated circuit (IC) chips. In the method, wafers are received and the backside roughness levels of these wafers are...
2016/0181165 METHOD AND APPARATUS FOR REAL-TIME MONITORING OF PLASMA ETCH UNIFORMITY
A method is provided for in-situ monitoring of etch uniformity during plasma etching, on the basis of the detection of interferometry patterns. The method is...
2016/0181164 FIN FORMATION ON AN INSULATING LAYER
An approach to forming fins for a semiconductor device on a silicon-on-insulator wafer. The approach includes depositing a layer of mandrel material and...
2016/0181163 Method and Structure for Metal Gates
A semiconductor device having metal gates and methods of forming the same are disclosed. The method includes receiving a substrate, a dummy gate stack formed...
2016/0181162 GATE-ALL-AROUND FIN DEVICE
A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a...
2016/0181161 SUB-FIN DEVICE ISOLATION
A fin-based structure may include fins on a surface of a semiconductor substrate. Each of the fins may include a doped portion proximate to the surface of the...
2016/0181160 METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE
When a gate insulating film is formed on a silicon carbide substrate, the silicon carbide substrate is first oxidized with an oxidation reactant gas to form...
2016/0181159 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
A method for fabricating a semiconductor device, including forming gate patterns over a substrate, forming conductive layer covering top and sidewalls of each...
2016/0181158 METHOD AND STRUCTURE FOR A LARGE-GRAIN HIGH-K DIELECTRIC
A method of forming a semiconductor device (100) includes depositing a metal oxide (104) over the substrate (102). The depositing includes combining a first...
2016/0181157 Through Silicon Via Structure and Method
A system and method for manufacturing a through silicon via is disclosed. An embodiment comprises forming a through silicon via with a liner protruding from a...
2016/0181156 SELF-ALIGNED INTERCONNECTION FOR INTEGRATED CIRCUITS
Methods and structures provide horizontal conductive lines of fine pitch and self-aligned contacts extending from them, where the contacts have at least one...
2016/0181155 METHOD FOR MAKING AN INTEGRATED CIRCUIT IN THREE DIMENSIONS
Method of making an integrated circuit, comprising at least the following steps: a) form a first semiconducting or conducting element, covered with a first...
2016/0181154 SEMICONDUCTOR DEVICE WITH MULTI-LAYER METALLIZATION
One or more embodiments are related to a semiconductor device, comprising: a metallization layer comprising a plurality of portions, each of the portions...
2016/0181153 INTEGRATED CIRCUIT BARRIERLESS MICROFLUIDIC CHANNEL
A structure and method for fabricating a continuous cooling channel in the back end of line wiring levels of an integrated circuit (IC) chip is provided. This...
2016/0181152 Semiconductor Device Metallization Systems and Methods
Semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a...
2016/0181151 TITANIUM TUNGSTEN LINER USED WITH COPPER INTERCONNECTS
Approaches for providing a liner at a via-to-wire interface are provided. A method includes: forming a via opening that exposes an upper surface of a copper...
2016/0181150 Precursors Of Manganese And Manganese-Based Compounds For Copper Diffusion Barrier Layers And Methods Of Use
Semiconductor devices and methods of making semiconductor devices with a barrier layer comprising manganese nitride are described. Also described are...
2016/0181149 SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
A method for forming a semiconductor structure is provided. The method includes providing a substrate; and forming an ultra-low-dielectric-constant (ULK)...
2016/0181148 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
In one embodiment, a semiconductor device includes a substrate, first and second interconnects provided on the substrate to be apart from each other, and third...
2016/0181147 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A first MISFET which is a semiconductor element is formed on an SOI substrate. The SOI substrate includes a supporting substrate which is a base, BOX layer...
2016/0181146 SHALLOW TRENCH ISOLATIONS AND METHOD OF MANUFACTURING THE SAME
A method of manufacturing shallow trench isolations is provided in the present invention, which includes the steps of providing a substrate, performing a zero...
2016/0181145 LAND SIDE AND DIE SIDE CAVITIES TO REDUCE PACKAGE Z-HEIGHT
A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die...
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