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Patent # Description
2016/0181144 METHOD FOR MANUFACTURING INTERCONNECT STRUCTURES INCORPORATING AIR GAP SPACERS
A dual damascene article of manufacture comprises a trench containing a conductive metal column where the trench and the conductive metal column extend down...
2016/0181143 SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD FOR FABRICATING THE SAME
A method for fabricating a semiconductor device includes preparing a substrate which includes a memory cell region and a peripheral circuit region; forming a...
2016/0181142 EDGE RING FOR A SUBSTRATE PROCESSING CHAMBER
An edge ring and process for fabricating an edge ring are disclosed herein. In one embodiment, an edge ring includes an annular body and a plurality of thermal...
2016/0181141 WAFER PROCESSING METHOD
A wafer is divided into individual device chips along division lines. A modified layer is formed by applying a laser beam having a transmission wavelength to...
2016/0181140 PROTECTIVE TAPE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME
A protective tape and a method for manufacturing a semiconductor device using the same capable of achieving excellent connection properties. The protective...
2016/0181139 METHOD OF TRANSFORMING AN ELECTRONIC DEVICE
There is provided a method for transforming an electronic device from an initial state, wherein the device includes a first substrate and a second substrate,...
2016/0181138 Method of manufacturing a semiconductor component and semiconductor component
Various embodiments provide method of manufacturing a semiconductor component, wherein the method comprises providing a layer stack comprising a carrier and a...
2016/0181137 SUPPORTING UNIT AND SUBSTRATE TREATING APPARATUS INCLUDING THE SAME
A fabrication method of a supporting unit supporting a substrate is provided. The fabrication method includes providing a supporting plate that is made of a...
2016/0181136 PACKAGING APPARATUS AND PACKAGING DEVICE
The present invention discloses a packaging apparatus and a packaging device. The packaging apparatus comprises a mask plate and a control circuit that is...
2016/0181135 SYSTEM AND METHOD FOR MOVING WORKPIECES BETWEEN MULTIPLE VACUUM ENVIRONMENTS
Provided are approaches for transferring workpieces between multiple pressure environments. In one approach, a system for moving workpieces between a first...
2016/0181134 MONITORING SYSTEM FOR DEPOSITION AND METHOD OF OPERATION THEREOF
A monitoring and deposition control system and method of operation thereof including: a deposition chamber for depositing a material layer on a substrate; a...
2016/0181133 SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD
A substrate processing apparatus includes a hot plate which supports and heats a substrate, a light source which emits etching energy beam such that the...
2016/0181132 Apparatus For Improving Temperature Uniformity Of A Workpiece
An apparatus and method for improving the temperature uniformity of a workpiece during processing is disclosed. The apparatus includes a ring heater assembly...
2016/0181131 PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD
Provided are a plasma processing apparatus with a radio-frequency power supply supplying temporally modulated intermittent radio-frequency power which can be...
2016/0181130 INTERNAL PLASMA GRID FOR SEMICONDUCTOR FABRICATION
The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a...
2016/0181129 DEVICE FOR MEASURING THE DISTRIBUTION OR IMPULSE OF A SERIES OF DROPLETS
A device for measuring the distribution and/or impulse of a series of droplets comprises a piezoelectric sensor positioned relative to a source of droplets...
2016/0181128 HIGH-THROUGHPUT SEMICONDUCTOR-PROCESSING APPARATUS EQUIPPED WITH MULTIPLE DUAL-CHAMBER MODULES
A wafer-processing apparatus includes: multiple discrete units of reactors disposed on the same plane; a wafer-handling chamber having a polygonal shape having...
2016/0181127 METHOD FOR COUPLING CIRCUIT ELEMENT AND PACKAGE STRUCTURE
A method for coupling an circuit element onto a carrier element includes steps of providing the circuit element having a front side, a back side, and at least...
2016/0181126 METHOD FOR MANUFACTURING MULTI-CHIP PACKAGE
A multi-chip package structure is provided, including a substrate having a grounding structure; two semiconductor elements disposed on and electrically...
2016/0181125 STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH THERMAL SPACERS AND ASSOCIATED SYSTEMS AND METHODS
Stacked semiconductor die assemblies with thermal spacers and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die...
2016/0181124 3D Packages and Methods for Forming the Same
Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device...
2016/0181123 METHOD OF PRODUCING BONDED BODY AND METHOD OF PRODUCING POWER MODULE SUBSTRATE
A method of producing a bonded body is disclosed in which a ceramic member made of ceramics and a Cu member made of Cu or a Cu alloy are bonded to each other,...
2016/0181122 MAKING A FLAT NO-LEAD PACKAGE WITH EXPOSED ELECTROPLATED SIDE LEAD SURFACES
A method of making Flat No-Lead Packages with plated lead surfaces exposed on lateral faces thereof. The method includes providing a plurality of Flat No-Lead...
2016/0181121 ELECTRO-ASSISTED TRANSFER AND FABRICATION OF WIRE ARRAYS
A fabrication method includes: (1) forming a wire array on a fabrication substrate; (2) forming a porous layer within a portion of the fabrication substrate...
2016/0181120 Laser annealing systems and methods with ultra-short dwell times
Laser annealing systems and methods with ultra-short dwell times are disclosed. The method includes locally pre-heating the wafer with a pre-heat line image...
2016/0181119 PLASMA ETCHING METHOD
A plasma etching method includes a first process of applying, while applying a first high frequency power to a lower electrode, a second high frequency power...
2016/0181118 PLASMA PROCESSING METHOD
A plasma processing method capable of controlling an etching rate of a SiN film and obtaining high selectivity to a SiO.sub.2 film and Si at the same time...
2016/0181117 INTEGRATED ETCH/CLEAN FOR DIELECTRIC ETCH APPLICATIONS
The embodiments herein relate to methods and apparatus for etching a recessed feature in dielectric material. In various embodiments, a recessed feature is...
2016/0181116 SELECTIVE NITRIDE ETCH
Methods of selectively etching silicon nitride are provided. Silicon nitride layers are exposed to a fluorinating gas and nitric oxide (NO), which may be...
2016/0181115 Method of Forming a Mask for Substrate Patterning
Techniques herein include using acid-diffusion--controllable to specific diffusion lengths--to create sacrificial structures that, when removed, define a...
2016/0181114 Method for Fabricating Multiple Layers of Ultra Narrow Silicon Wires
A method for preparing a multilayer superfine silicon line, comprising: preparing an etching masking layer of silicon; forming a fin and source/drain region on...
2016/0181113 METHOD FOR FORMING STAIR-STEP STRUCTURES
A method for forming a stair-step structure in a substrate is provided. An organic mask is formed over the substrate. A hardmask with a top layer and sidewall...
2016/0181112 ANISOTROPIC GAP ETCH
A method of anisotropically dry-etching exposed substrate material on a patterned substrate is described. The patterned substrate has a gap formed in a single...
2016/0181111 SILICON ETCH AND CLEAN
A method for etching features into a silicon containing etch layer is provided. The etch layer is placed into a plasma processing chamber. An etch gas is...
2016/0181110 Lithographic Technique for Feature Cut by Line-End Shrink
A technique for patterning a workpiece such as an integrated circuit workpiece is provided. In an exemplary embodiment, the method includes receiving a dataset...
2016/0181109 SEMICONDUCTOR DEVICE MANUFACTURING METHOD
A semiconductor device manufacturing method includes forming a dielectric film on a semiconductor substrate; forming a resist pattern on the dielectric film;...
2016/0181108 Doping of High-K Dielectric Oxide by Wet Chemical Treatment
A method for fabricating a semiconductor device includes forming a first high-k (HK) dielectric layer over a substrate, performing a wet treatment process to...
2016/0181107 METHOD FOR ETCHING HIGH-K METAL GATE STACK
A method for etching a gate includes forming a high-k material layer over a substrate; forming an overlying layer over the high-k material layer; performing a...
2016/0181106 Phase Change Memory with Diodes Embedded in Substrate
An integrated circuit structure includes a semiconductor substrate; a diode; and a phase change element over and electrically connected to the diode. The diode...
2016/0181105 SILICON-GERMANIUM (SiGe) FIN FORMATION
Constructing an SiGe fin by: (i) providing an intermediate sub-assembly including a silicon-containing base layer and a silicon-containing first fin structure...
2016/0181104 Method for Forming a Semiconductor Device and a Semiconductor Substrate
A method for forming a semiconductor device includes incorporating chalcogen dopant atoms into a semiconductor doping region of a semiconductor substrate of a...
2016/0181103 SEMICONDUCTOR DEVICE INCLUDING SMALL PITCH PATTERNS
A method is provided for fabricating small pitch patterns. The method includes providing a semiconductor substrate, and forming a target material layer having...
2016/0181102 HARD-MASK DEFINED BIT PATTERN SUBSTRATE
Provided is an apparatus that includes a substrate; a first hard-mask pattern that includes a number of first features disposed over a top surface of the...
2016/0181101 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a plurality of line patterns including at least two continuous line repetition units having, as one of the line repetition...
2016/0181100 Patterning a Substrate Using Grafting Polymer Material
Patterning methods for creating sub-resolution trenches, contact openings, lines, and other structures at smaller dimensions as compared to using conventional...
2016/0181099 METHODS AND STRUCTURES TO PREVENT SIDEWALL DEFECTS DURING SELECTIVE EPITAXY
Trenches (and processes for forming the trenches) are provided that reduce or prevent crystaline defects in selective epitaxial growth of type III-V or...
2016/0181098 OXIDE SEMICONDUCTOR LAYER AND PRODUCTION METHOD THEREFOR, OXIDE SEMICONDUCTOR PRECURSOR, OXIDE SEMICONDUCTOR...
The invention provides an oxide semiconductor layer that has less cracks and is excellent in electrical property and stability, as well as a semiconductor...
2016/0181097 Epitaxial Growth Techniques for Reducing Nanowire Dimension and Pitch
Techniques for reducing nanowire dimension and pitch are provided. In one aspect, a pitch multiplication method for nanowires includes the steps of: providing...
2016/0181096 Method For Growing Germanium Epitaxial Films
A method for growing germanium epitaxial films is disclosed. Initially, a silicon substrate is preconditioned with hydrogen gas. The temperature of the...
2016/0181095 SILICON-GERMANIUM FIN OF HEIGHT ABOVE CRITICAL THICKNESS
Embodiments of the invention include a method for fabricating a SiGe fin and the resulting structure. A SOI substrate is provided, including at least a silicon...
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