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Patent # Description
2016/0180943 SENSING CIRCUIT FOR A NON-VOLATILE MEMORY CELL HAVING TWO COMPLEMENTARY MEMORY TRANSISTORS
Voltage is increased on a wordline signal. The wordline signal is applied to a programmed FET and an unprogrammed FET of a memory cell. The programmed FET has...
2016/0180942 STORAGE DEVICE, NONVOLATILE MEMORY AND METHOD OPERATING SAME
A method of operating a storage device includes; counting a number of fast cycles for the memory block when a program interval between two successive program...
2016/0180941 SEMICONDUCTOR DEVICE
A memory array (101) includes a plurality of twin cells (104), each of which is composed of a first memory element (102) and a second memory element (103)...
2016/0180940 SEMICONDUCTOR DEVICE
A semiconductor device is provided. The semiconductor device includes a memory block including memory cells connected to word lines, and an operation circuit...
2016/0180939 Time Domain Ramp Rate Control for Erase Inhibit in Flash Memory
When performing an erase on a flash type non-volatile memory with a NAND type of structure, techniques are presented for inhibiting erase on selected word...
2016/0180938 MEMORY SYSTEM
According to an embodiment, a memory system includes first wiring lines; second wiring lines; third wiring lines; fourth wiring lines; and first and second...
2016/0180937 NONVOLATILE MEMORY DEVICE AND DRIVING METHOD THEREOF
According to example embodiments, a nonvolatile memory device includes a plurality of strings having a plurality of serially-connected selection transistors...
2016/0180936 MEMORY SYSTEM AND OPERATING METHOD THEREOF
A memory system includes a memory device including a plurality of memory blocks each including a plurality of pages, wherein the plurality of pages each...
2016/0180935 VOLTAGE SWITCHING CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME
A voltage switching circuit includes: a control signal generation block configured to include a high voltage switching block which controls an electric current...
2016/0180934 APPARATUS, SYSTEMS, AND METHODS TO OPERATE A MEMORY
Various embodiments, disclosed herein, include apparatus and methods to read a logic level in a selected memory cell in a selected string of a memory by...
2016/0180933 METHODS AND APPARATUSES HAVING A VOLTAGE GENERATOR WITH AN ADJUSTABLE VOLTAGE DROP FOR REPRESENTING A VOLTAGE...
Apparatus and methods utilize a replica circuit to generate a voltage for programming of a memory cell, such as a memory cell of a phase-change memory (PCM)....
2016/0180932 SYSTEMS, AND DEVICES, AND METHODS FOR PROGRAMMING A RESISTIVE MEMORY CELL
Embodiments disclosed herein may relate to programming a memory cell with a programming pulse that comprises a quenching period having different portions. The...
2016/0180931 APPARATUSES AND/OR METHODS FOR OPERATING A MEMORY CELL AS AN ANTI-FUSE
Embodiments disclosed herein relate to operating a memory cell as an anti-fuse, such as for use in phase change memory, for example.
2016/0180930 SEMICONDUCTOR STORAGE DEVICE
A semiconductor storage device according to an embodiment comprises a plurality of column power supply lines and a plurality of row power supply lines. A...
2016/0180929 Variable Resistance Memory Device
A variable resistance memory device includes upper interconnections on a substrate, first and second word lines provided between the substrate and the upper...
2016/0180928 ELECTRONIC DEVICE AND OPERATING METHOD FOR THE SAME
An electronic device includes a semiconductor memory unit. The semiconductor memory unit may include a cell array suitable for including a plurality of...
2016/0180927 METHOD FOR INCREASING SPEED OF WRITING DATA INTO FLASH MEMORY UNIT AND ASSOCIATED DEVICE
A method for writing data into a flash memory unit includes: when writing data into the flash memory unit for the n-th time, determining a data polarity of an...
2016/0180926 NONVOLATILE MEMORY SYSTEM STORING SYSTEM DATA IN MARGINAL WORD LINES
To make more efficient use of storage capacity, a non-volatile storage system will store system data on marginal word lines. In one embodiment, a marginal word...
2016/0180925 VOLATILE/NON-VOLATILE SRAM DEVICE
A method of operation of a static random access memory (SRAM) storage element includes programming a value to the SRAM storage element prior to a power-down...
2016/0180924 METHOD AND APPARATUS FOR REDUCING LEAKAGE CURRENT IN MEMORY
A method and apparatus in which word line drivers associated with memory word lines are selectively powered based on an active memory address reduces current...
2016/0180923 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND WEARABLE DEVICE
To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a...
2016/0180922 MULTI-STATE CONFIGURATION RAM CELL
A multi-state static RAM cell includes N NOR gates. Each NOR gate has N-1 inputs and one output. The output of each NOR gate is coupled to a different bit...
2016/0180921 SEMICONDUCTOR MEMORY DEVICE CONTROLLING REFRESH CYCLE, MEMORY SYSTEM, AND METHOD OF OPERATING THE SEMICONDUCTOR...
A semiconductor memory device includes a memory cell array, a refresh control circuit, an address counter and an address converter. The memory cell array...
2016/0180920 REFRESH REQUEST QUEUING CIRCUITRY
An apparatus and system associated with memory are disclosed herein. In various embodiments, an apparatus may include first circuitry to determine a number of...
2016/0180919 MULTI-CHANNEL SELF REFRESH DEVICE
A multi-channel self refresh device may include period generation circuit configured to output a self refresh pulse signal having a predetermined time period...
2016/0180918 SEMICONDUCTOR DEVICE, MEMORY ACCESS CONTROL METHOD, AND SEMICONDUCTOR DEVICE SYSTEM
A semiconductor device (100) according to an embodiment calculates the number of times of burst access for an address set (A) based on a result of a...
2016/0180917 Techniques to Reduce Memory Cell Refreshes for a Memory Device
Examples may include techniques to reduce memory cell refreshes for a memory device. These techniques include a control unit receiving a command to cause an...
2016/0180916 Reconfigurable Row Dram
Technologies are generally described herein for a reconfigurable row dynamic random access memory device. The reconfigurable row may correspond to a logically...
2016/0180915 SEMICONDUCTOR MEMORY DEVICE INCLUDING A CIRCUIT FOR STORING AN OPERATING STATE AND SEMICONDUCTOR SYSTEM HAVING...
A semiconductor memory device may include: a data alignment signal generation unit suitable for generating an alignment signal corresponding to an input speed...
2016/0180914 SEMICONDUCTOR DEVICE AND METHOD OF DRIVING THE SAME
A semiconductor device includes: a control block suitable for generating a clock control signal in response to a write training signal and a write-related...
2016/0180913 DIFFERENTIAL VECTOR STORAGE FOR DYNAMIC RANDOM ACCESS MEMORY
A storage device stores data in groups of memory cells using vectors corresponding to voltage code codewords, each codeword having k entries. Entries have...
2016/0180912 SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM WITH THE SEMICONDUCTOR DEVICE AND METHOD OF DRIVING THE...
A semiconductor device includes a first control block suitable for selectively blocking a refresh command signal based on a period signal having a...
2016/0180911 METHOD OF WRITING TO A SPIN TORQUE MAGNETIC RANDOM ACCESS MEMORY
Circuitry and methods provide an increased tunnel barrier endurance (lifetime) previously shortened by dielectric breakdown by providing a charging pulses of...
2016/0180910 WORD LINE AUTO-BOOTING IN A SPIN-TORQUE MAGNETIC MEMORY HAVING LOCAL SOURCE LINES
In a spin-torque magnetic random access memory (MRAM) that includes local source lines, auto-booting of the word line is used to conserve power consumption by...
2016/0180909 WRITE OPERATIONS IN SPIN TRANSFER TORQUE MEMORY
Apparatus, systems, and methods for write operations in spin transfer torque (STT) memory are described. In one embodiment, a memory comprises at least one...
2016/0180908 UNIPOLAR-SWITCHING PERPENDICULAR MRAM AND METHOD FOR USING SAME
MRAM devices that are switched by unipolar electron flow are described. Embodiments use arrays of cells that include a diode or transistor with a pMTJ. The...
2016/0180907 METHOD FOR COMPUTING WITH COMPLEMENTARY NETWORKS OF MAGNETIC TUNNEL JUNCTIONS
A magnetic tunnel junction (MTJ) device is provided that includes a MTJ element and a control wire. The MTJ element includes a top ferromagnet layer formed of...
2016/0180906 MAGNETIC RECORDING APPARATUS
According to one embodiment, a magnetic recording apparatus includes a spin-torque oscillator, a recording unit, and a controller. The spin-torque oscillator...
2016/0180905 ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME
Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: an under layer including first and second metal layers...
2016/0180904 MEMORY DEVICE
A memory device includes a memory bank including a plurality of word lines, and a word line controller capable of activating a first word line, which is...
2016/0180903 MEMORY OPERATION LATENCY CONTROL
An integrated circuit with memory can operate with reduced latency between consecutive operations such as read operations. At a first time, a first operation...
2016/0180902 SEMICONDUCTOR MEMORY DEVICE
A circuit of a semiconductor memory device may include a delay unit suitable for delaying a column pulse signal, and sequentially generating a first strobe...
2016/0180901 DATA STROBING CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE SAME
A data strobing circuit may include: an operating speed detection unit configured to detect an operating speed of a semiconductor apparatus according to a...
2016/0180900 IMPLEMENTING DRAM ROW HAMMER AVOIDANCE
A method and apparatus for implementing row hammer avoidance in a dynamic random access memory (DRAM) in a computer system. Hammer detection logic identifies a...
2016/0180899 IMPLEMENTING DRAM ROW HAMMER AVOIDANCE
A method and apparatus for implementing row hammer avoidance in a dynamic random access memory (DRAM) in a computer system. Hammer detection logic identifies a...
2016/0180898 MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME
A memory controller for controlling a flash memory device is provided. The memory controller generates pattern data, a program command, and a read command,...
2016/0180897 DRIVER STRUCTURE FOR CHIP-TO-CHIP COMMUNICATIONS
Apparatus for chip-to-chip communications may include a first driving unit and a second driving unit. The first driving unit may receive input data, generate a...
2016/0180896 MEMORY WITH MULTIPLE WRITE PORTS
A memory 2 includes a regular array of storage elements 4. A regular array of write multiplexers 8 is provided outside of the regular array of storage elements...
2016/0180895 SEMICONDUCTOR MEMORY APPARATUS AND DATA TRANSMISSION
A semiconductor memory apparatus may include a data pad and a shared transmission line. The shared transmission line may be configured to transmit data...
2016/0180894 DIFFERENTIAL SENSING CIRCUIT WITH DYNAMIC VOLTAGE REFERENCE FOR SINGLE-ENDED BIT LINE MEMORY
The present invention provides a differential sensing circuit with a dynamic voltage reference for a single-ended bit line memory is disclosed. The exemplary...
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