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Patent # Description
2016/0179743 SYSTEMS, METHODS, AND DEVICES FOR MEDIA AGNOSTIC USB PACKET SCHEDULING
Example systems, methods, and devices for scheduling traffic by a media agnostic universal serial bus protocol adaptive layer. In one embodiment, a method can...
2016/0179742 METHOD AND APPARATUS FOR PROVIDING A HOST MEMORY CONTROLLER WRITE CREDITS FOR WRITE COMMANDS
Provided are a method and apparatus for providing a host memory controller write credits for write commands. A host memory controller coupled to a memory...
2016/0179741 DYNAMIC LANE MANAGEMENT FOR INTERFERENCE MITIGATION
Dynamic lane management for interference mitigation is disclosed. In one aspect, an integrated circuit (IC) is provided that employs a control system...
2016/0179740 HIGH PERFORMANCE INTERCONNECT
A signal is received, a boundary of which is to be sent in alignment with a sync counter value. A nominal latency of a link is determined based on the sync...
2016/0179739 SYMMETRICALLY COUPLED DIFFERENTIAL CHANNEL
A stream of binary data is converted into a stream of symbols according to a three-phase encoding scheme and send the symbols on a physical link. The link...
2016/0179738 METHOD, APPARATUS AND SYSTEM FOR INTEGRATING DEVICES IN A ROOT COMPLEX
In an embodiment, an apparatus comprises: a semiconductor die including but not limited to: at least one core to execute instructions; an agent to perform at...
2016/0179737 PIN-CONFIGURABLE INTERNAL BUS TERMINATION SYSTEM
A pin-configurable bus termination system may includes a bus connector attached to an end of a bus. The bus connector may be configured for electrically...
2016/0179736 CHIP PROCESSING DEVICE AND METHOD FOR CHIP PROCESSING USING THE SAME
The present invention provides a chip processing device and a method for chip processing using the same, where the device can program, detect, reset or inspect...
2016/0179735 MANAGING A PERIPHERAL COMPONENT INTERFACE EXPRESS DEVICE HOTPLUG
Embodiment of the present disclosure provides a system, a computer program product and a method for managing a peripheral component interface express device...
2016/0179734 METHOD AND SYSTEM FOR HOT-PLUG FUNCTIONS
Embodiments generally relate to hot-plug technology. The present technology discloses hardware and software specifications that can enable hot-plug functions...
2016/0179733 TWO-PART ELECTRICAL CONNECTOR
A two-part electrical connector includes a bottom connector and a top connector. The bottom connector includes a set of electrical contacts, at least one of...
2016/0179732 CONNECTION DEVICE
A connecting device comprises housing, a board with electrical components, including at least one digital bus connection and an input/output section. It allows...
2016/0179731 DATA COMMUNICATIONS SYSTEM AND METHOD OF DATA TRANSMISSION
A 1553 data communication system having a primary data bus, a redundant data bus and a non-1553 data communication overlay system is provided. The non-1553...
2016/0179730 HIGH PERFORMANCE INTERCONNECT LINK STATE TRANSITIONS
A supersequence is sent to another device to indicate a transition from a partial width link state to another active link state. The supersequence is to be...
2016/0179729 INPUT/OUTPUT SWTICHING MODULE INTERFACE IDENTIFICATION IN A MULTI-SERVER CHASSIS
An interface identification system includes an IHS enclosure including a plurality of IHS slots and a plurality of input/output (I/O) switching module slots. A...
2016/0179728 HIGH BANDWIDTH CORE TO NETWORK-ON-CHIP INTERFACE
An apparatus includes a first port set that includes an input port and an output port. The apparatus further includes a plurality of second port sets. Each of...
2016/0179727 PERIPHERAL COMPONENT INTERFACE (PCI) SYSTEM AND METHOD FOR EXPANDING PCI NODES IN AN INFORMATION HANDLING SYSTEM
An information handling system (IHS), peripheral component interface (PCI) system and method for expanding PCI nodes in an IHS. The PCI system includes a...
2016/0179726 PROGRAMMING HARDWARE REGISTERS USING A PIPELINED REGISTER BUS, AND RELATED METHODS, SYSTEMS, AND APPARATUSES
Programming hardware registers using a pipelined register bus, and related methods, systems, and apparatuses are disclosed. In one aspect, a method for...
2016/0179725 INPUT/OUTPUT METHOD IN VIRTUAL MACHINE ENVIRONMENTS
A input/output method is disclosed for performing communications in a virtual machine (VM) environment between a host operating system (OS) and a guest OS. The...
2016/0179724 INTERFACE MODULE
An interface module has at least a configuration connection, a reset connection, a transmission connection and a reception connection. The interface module...
2016/0179723 COMMUNICATION SYSTEM, MANAGEMENT APPARATUS, AND CONTROLLING APPARATUS
A communication system includes a communication apparatus comprising a plurality of first connectors; a controlling apparatus that comprises a plurality of...
2016/0179722 ELECTRONIC DEVICE AND METHOD FOR COMMUNICATING WITH USB DEVICE
According to one embodiment, an electronic device includes a USB host controller, and a wireless transceiver connected to the USB host controller through a USB...
2016/0179721 DELIVERING INTERRUPTS TO USER-LEVEL APPLICATIONS
Systems and methods for delivering interrupts to user-level applications. An example processing system comprises: a memory configured to store a plurality of...
2016/0179720 DEVICE TABLE IN SYSTEM MEMORY
Embodiments relate to an implementation of a device table in system memory to which a peripheral component interface (PCI) adapter is coupled via a host...
2016/0179719 COMPUTER SYSTEM, A SYSTEM MANAGEMENT MODULE AND METHOD OF BIDIRECTIONALLY INTERCHANGING DATA
A computer system includes a system component with at least one expansion bus and at least one processor coupled to the at least one expansion bus and executes...
2016/0179718 EARLY IDENTIFICATION IN TRANSACTIONAL BUFFERED MEMORY
A sequence of read returns are to be sent to a host device over a transactional buffered memory interface, where the sequence includes at least a first read...
2016/0179717 SYSTEM ON A CHIP COMPRISING RECONFIGURABLE RESOURCES FOR MULTIPLE COMPUTE SUB-SYSTEMS
Embodiments of the technology can provide the flexibility of fine-grained dynamic partitioning of various compute resources among different compute subsystems...
2016/0179716 TIMER MANAGEMENT APPARATUS
Disclosed herein is a timer management apparatus in which contiguous timer interrupts of an operating system run on IT equipment (desktop computers, servers,...
2016/0179715 SYNCHRONOUS BUS ARCHITECTURE FOR DIGITAL PRE-DISTORTION SYSTEM
A system for storing pre-distorted output samples in a memory includes a sample counter, a programming interface module, and a comparator. The sample counter...
2016/0179714 TRACE BUFFER BASED REPLAY FOR CONTEXT SWITCHING
A command processor may process a command stream for execution by at least one processor, including storing data associated with a first set of one or more...
2016/0179713 SEMICONDUCTOR INTEGRATED CIRCUIT AND DEVICE DETECTION SYSTEM PROVIDED WITH THE SAME
Provided is a semiconductor integrated circuit capable of reducing power consumption while continuously detecting presence of connection of a device. The...
2016/0179712 Categorizing Memory Pages Based On Page Residences
Embodiments of the present invention provide hints for page stealing by prioritizing pages based on the number of residences. Receiving a plurality of pages to...
2016/0179711 CONGESTION CONTROL IN STORAGE SYSTEMS
An I/O request directed to a portion of a storage object managed at a distributed storage service is received. A congestion control parameter value to be used...
2016/0179710 PHYSICAL INTERFACE FOR A SERIAL INTERCONNECT
An apparatus that includes a physical interface for a serial interconnect is provided. The physical interface includes a buffer that is selectable to function...
2016/0179709 PROCESSING ELEMENT DATA SHARING
A memory sharing method and system in a distributed computing environment. The method includes placing a first operator and a second operator within a...
2016/0179708 INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM
An information processing apparatus includes first and second central processing units, a communication unit, and a memory. The first and second central...
2016/0179707 Sharing a Common Resource Via Multiple Interfaces
In one embodiment, an electronic system includes a shared resource and multiple controllers connected to the shared resource by different resource interfaces....
2016/0179706 PAIRING OF EXTERNAL DEVICE WITH RANDOM USER ACTION
Certain embodiments herein relate to pairing an external device and a computer using a random user action. The random user action may be generated based on the...
2016/0179705 METHOD OF PROGRAMMING THE DEFAULT INTERFACE SOFTWARE IN AN INDICIA READING DEVICE
An indicia reading apparatus includes an NFC module and an indicia reading device. The indicia reading device is configured so that, if the indicia reader...
2016/0179704 System and Method for Providing Kernel Intrusion Prevention and Notification
A memory protection module includes comparison logic that has a write-once window CSR that stores a memory address range, and window protection logic. The...
2016/0179703 METHOD AND DEVICE FOR SECURE PROCESSING OF ENCRYPTED DATA
A method for secure processing of encrypted data within a receiver comprising a memory and a configurable authorization filter for access to the memory, the...
2016/0179702 Memory Encryption Engine Integration
Memory encryption engine (MEE) integration technologies are described. A processor can include a processor core and an arbiter of a MEE system coupled to the...
2016/0179701 ADDRESS TRANSLATION CACHE THAT SUPPORTS SIMULTANEOUS INVALIDATION OF COMMON CONTEXT ENTRIES
A processor includes a mapping module that maps architectural virtual processor identifiers to non-architectural global identifiers and maps architectural...
2016/0179700 Hiding Page Translation Miss Latency in Program Memory Controller By Selective Page Miss Translation Prefetch
This invention hides the page miss translation latency for program fetches. In this invention whenever an access is requested by CPU, the L1I cache controller...
2016/0179699 HIDING PAGE TRANSLATION MISS LATENCY IN PROGRAM MEMORY CONTROLLER BY NEXT PAGE PREFETCH ON CROSSING PAGE BOUNDARY
This invention hides the page miss translation latency for program fetches. In this invention whenever an access is requested by CPU that crosses a memory page...
2016/0179698 TRACKING MEMORY ACCESSES WHEN INVALIDATING EFFECTIVE ADDRESS TO REAL ADDRESS TRANSLATIONS
According to embodiments of the present disclosure, a method for invalidating an address translation entry in an effective address to real address translation...
2016/0179697 MEMORY SYSTEM AND OPERATING METHOD THEREOF
A memory system includes a plurality of memory chips each including memory regions and page buffers; an address table suitable for storing mapping information...
2016/0179696 METHOD AND APPARATUS TO ALLOW SECURE GUEST ACCESS TO EXTENDED PAGE TABLES
An apparatus and method for efficient guest EPT manipulation. For example, one embodiment of a apparatus comprises: a hypervisor to create extended page table...
2016/0179695 Local Page Translation and Permissions Storage for the Page Window in Program Memory Controller
This invention provides a current page translation register storing virtual to physical address translation data for a current page and optionally access...
2016/0179694 TRACKING MEMORY ACCESSES WHEN INVALIDATING EFFECTIVE ADDRESS TO REAL ADDRESS TRANSLATIONS
According to embodiments of the present disclosure, a method for invalidating an address translation entry in an effective address to real address translation...
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