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Patent # Description
2016/0179693 INSTRUCTION SET ARCHITECTURE WITH OPCODE LOOKUP USING MEMORY ATTRIBUTE
A circuit arrangement decodes instructions based in part on one or more decode-related attributes stored in a memory address translation data structure such as...
2016/0179692 MULTI-CORE PROGRAMMING APPARATUS AND METHOD FOR RESTORING DATA ARRAYS FOLLOWING A POWER GATING EVENT
An apparatus includes a programmer, a stores, and a plurality of cores. The programmer programs a fuse array with compressed configuration data. The stores...
2016/0179691 MULTI-CORE MICROPROCESSOR POWER GATING CACHE RESTORAL PROGRAMMING MECHANISM
An apparatus includes a device programmer and a stores. The device programmer programs a semiconductor fuse array with compressed configuration data for a...
2016/0179690 MULTI-CORE DATA ARRAY POWER GATING CACHE RESTORAL PROGRAMMING MECHANISM
An apparatus including a device programmer, a stores, and a plurality of cores. The device programmer programs a semiconductor fuse array with compressed...
2016/0179689 MULTI-CORE PROGRAMMING APPARATUS AND METHOD FOR RESTORING DATA ARRAYS FOLLOWING A POWER GATING EVENT
An apparatus includes a device programmer and a plurality of cores. The programmer programs a semiconductor fuse array with compressed configuration data. Each...
2016/0179688 SIMULTANEOUS INVALIDATION OF ALL ADDRESS TRANSLATION CACHE ENTRIES ASSOCIATED WITH X86 PROCESS CONTEXT IDENTIFIER
A translation-lookaside buffer (TLB) includes a plurality of entries, wherein each entry of the plurality of entries is configured to hold an address...
2016/0179687 UPDATING PERSISTENT DATA IN PERSISTENT MEMORY-BASED STORAGE
A processor includes a processing core to execute an application including instructions encoding a transaction with a persistent memory via a volatile cache...
2016/0179686 MEMORY MANAGEMENT METHOD FOR SUPPORTING SHARED VIRTUAL MEMORIES WITH HYBRID PAGE TABLE UTILIZATION AND RELATED...
A memory management method includes: checking shared virtual memory (SVM) support ability of at least one device participating in data access of a buffer;...
2016/0179685 DATA PROCESSING SYSTEM AND OPERATING METHOD THEREOF
A data processing system includes a host device configured to transmit a read/write command which includes data information of data corresponding to a data...
2016/0179684 NONVOLATILE MEMORY DEVICE AND OPERATING METHOD THEREOF
A nonvolatile memory device may include a memory area suitable for performing a cache operation in response to a command, a memory controller suitable for...
2016/0179683 SSD CACHING SYSTEM FOR HYBRID STORAGE
A SSD caching system for hybrid storages is disclosed. The caching system for hybrid storages includes: a Solid State Drive (SSD) for storing cached data,...
2016/0179682 ALLOCATING CACHE MEMORY ON A PER DATA OBJECT BASIS
Systems, methods, and software described herein allocate cache memory to job processes executing on a processing node. In one example, a method of allocating...
2016/0179681 ADJUSTABLE OVER-RESTRICTIVE CACHE LOCKING LIMIT FOR IMPROVED OVERALL PERFORMANCE
Disclosed is a cache locking system that includes a cache controller that is operable to receive a first request from a device to lock a first way in the...
2016/0179680 SYSTEMS AND METHODS FOR INTEGRATED ROTATION OF PROCESSOR CORES
In accordance with embodiments of the present disclosure, a processor may include a plurality of cores integrated within an integrated circuit package and a...
2016/0179679 SPECULATIVE READS IN BUFFERED MEMORY
A speculative read request is received from a host device over a buffered memory access link for data associated with a particular address. A read request is...
2016/0179678 NON-VOLATILE MEMORY CONTROLLER CACHE ARCHITECTURE WITH SUPPORT FOR SEPARATION OF DATA STREAMS
A system according to one embodiment includes non-volatile memory, and a non-volatile memory controller having a cache. An architecture of the cache supports...
2016/0179677 RESOLVING MEMORY ACCESSES CROSSING CACHE LINE BOUNDARIES
An instruction in a first cache line may be identified and an address associated with the instruction may be determined. The address may be determined to cross...
2016/0179676 CLEANING A WRITE-BACK CACHE
A data processing system incorporates a write-back cache and supports load-and-clean program instructions. The action of a load-and-clean program instruction...
2016/0179675 GRANULAR CACHE REPAIR
Systems and methods for granular cache repair. An example processing system comprises a processing core communicatively coupled to a cache via a cache...
2016/0179674 HARDWARE APPARATUSES AND METHODS TO CONTROL CACHE LINE COHERENCE
Methods and apparatuses to control cache line coherence are described. A hardware processor may include a first processor core with a cache to store a cache...
2016/0179673 CROSS-DIE INTERFACE SNOOP OR GLOBAL OBSERVATION MESSAGE ORDERING
Methods and apparatus relating to techniques for Cross-Die Interface (CDI) snoop and/or go (or completion) message ordering are described. In one embodiment,...
2016/0179672 MIRRORING A CACHE HAVING A MODIFIED CACHE STATE
A memory system includes multiple levels of cache and an auxiliary storage element for storing a copy of a cache line from one of the levels of cache when the...
2016/0179671 MIRRORING A CACHE HAVING A MODIFIED CACHE STATE
In one aspect a method includes determining, by a controller of a memory system, that a cache line of one of a plurality of levels of cache in the memory...
2016/0179670 POINTER CHASING ACROSS DISTRIBUTED MEMORY
A first pointer dereferencer receives a location of a portion of a first node of a data structure. The first node is to be stored in a first storage element. A...
2016/0179669 Method, Apparatus And Computer Programs Providing Cluster-Wide Page Management
A data processing system includes a plurality of virtual machines each having associated memory pages; a shared memory page cache that is accessible by each of...
2016/0179668 COMPUTING SYSTEM WITH REDUCED DATA EXCHANGE OVERHEAD AND RELATED DATA EXCHANGE METHOD THEREOF
A computing system includes a plurality of processing circuits and a storage device. The processing circuits have at least a first processing circuit and a...
2016/0179667 INSTRUCTION AND LOGIC FOR FLUSH-ON-FAIL OPERATION
A processor includes a memory management unit and a front end including a decoder. The decoder includes logic to receive a flush-on-commit (FoC) instruction to...
2016/0179666 Apparatus and Method to Dynamically Expand Associativity of A Cache Memory
In an embodiment, a processor includes at least one core, a cache memory, and a cache controller. Responsive to a request to store an address of a data entry...
2016/0179665 CONTROL OF ENTRY INTO PROTECTED MEMORY VIEWS
Generally, this disclosure provides systems, devices, methods and computer readable media for controlled memory view switching. The system may include a memory...
2016/0179664 PAGE-LEVEL HEALTH EQUALIZATION
According to one embodiment, a method includes assigning a subset of physical pages within a block of non-volatile memory to a pseudo-physical block, wherein a...
2016/0179663 SYSTEMS AND METHODS FOR GENERATING A UNIQUE DEVICE ID
A device including a network interface, a memory, and at least one processor is provided. The memory may include a random access memory (RAM) and nonvolatile...
2016/0179662 INSTRUCTION AND LOGIC FOR PAGE TABLE WALK CHANGE-BITS
A processor includes a binary translator, a memory management unit, and a monitor unit. The binary translator includes logic to translate a region of code and...
2016/0179661 MONITORING AND CAPTURING EARLY DIAGNOSTIC DATA
A deviance monitoring module is provided for examining various parameters of an operating system for deviance from a baseline behavior at specified intervals....
2016/0179660 Securing Secret Information in Source Code Verification and at Runtime
Source code verification, including receiving a declaration of a variable as a secret type, determining if any source code is configured to use the variable as...
2016/0179659 TECHNIQUES FOR AUTOMATICALLY GENERATING TESTCASES
A technique for generating testcases includes receiving a new product specification for an application. A noun-verb pairing is performed on the new product...
2016/0179658 USER INTERFACE TESTING ABSTRACTION
An automated test is identified for testing a software system including a graphical user interface (GUI) including a particular GUI element, where the...
2016/0179657 AUTO-DEPLOYMENT AND TESTING OF SYSTEM APPLICATION TEST CASES IN REMOTE SERVER ENVIRONMENTS
A method for executing a system application test case of a runtime system in an integrated server environment is provided. The method includes establishing a...
2016/0179656 AUTOMATICALLY TESTING FIRMWARE
Embodiments of the present disclosure provide a method and a system for automatically testing firmware by determining a contextual environment where a firmware...
2016/0179655 Automatic Switch To Debugging Mode
A system includes a processor and a memory comprising machine readable instructions that when executed by the processor, cause the system to receive command...
2016/0179654 ELAPSED TIME INDICATIONS FOR SOURCE CODE IN DEVELOPMENT ENVIRONMENT
Method and system are provided for providing elapsed time indications for source code in a development environment. The method includes: defining blocks of...
2016/0179653 SOURCE CODE EQUIVALENCE VERIFICATION DEVICE AND SOURCE CODE EQUIVALENCE VERIFICATION METHOD
When verifying rapidly the equivalence between source codes with respect to refactoring, the present invention performs two types of verification: verification...
2016/0179652 INTEGRATED PRODUCTION SUPPORT
Embodiments for integrating production support features are included in systems for receiving modules from a client application associated with an operator...
2016/0179651 ENABLING ERROR DETECTING AND REPORTING IN MACHINE CHECK ARCHITECTURE
In accordance with embodiments disclosed herein, there is provided systems and methods for detecting and reporting errors in a machine check environment. A...
2016/0179650 INSTRUCTION AND LOGIC FOR TRACKING ACCESS TO MONITORED REGIONS
A processor includes a front end, a decoder, a retirement unit, and a performance monitoring unit. The front end includes a decoder with logic to receive a...
2016/0179649 System for Security Conscious Energy Drain
A method, system and computer-usable medium are disclosed for detecting unanticipated consumption of power by a device. A first set of power consumption data...
2016/0179648 SYSTEM TO DETECT CHARGER AND REMOTE HOST FOR TYPE-C CONNECTOR
The present techniques include detecting a charger and remote host for a Type-C connector. An apparatus, system, and method are described herein. The apparatus...
2016/0179647 TEST LOGIC FOR A SERIAL INTERCONNECT
An apparatus that includes a serial interconnect is provided, wherein the serial interconnect includes test logic to send a number of reporting messages,...
2016/0179646 DELAYED AUTHENTICATION DEBUG POLICY
A chassis platform, such as processor or a system-on-chip (SoC), includes logic to implement a debug chassis security system including a policy generator to...
2016/0179645 SYSTEMS AND METHODS FOR FINE GRANULARITY MEMORY SPARING
Systems and methods for fine-grained sparing in non-volatile memories are disclosed. A system may include a memory having a plurality of blocks, a plurality of...
2016/0179644 MANAGEMENT OF STORAGE DEVICES
Embodiments of the present disclosure relate to a method, a computer program product and apparatus for management of a storage device by collecting bad storage...
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