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Patent # Description
2016/0179593 PUSH INSTRUCTION FOR PUSHING A MESSAGE PAYLOAD FROM A SENDING THREAD TO A RECEIVING THREAD
A processor core of a data processing system receives a push instruction of a sending thread that requests that a message payload identified by at least one...
2016/0179592 ADDRESSING FOR INTER-THREAD PUSH COMMUNICATION
In a data processing system, a switch includes a receive data structure including receive entries each uniquely corresponding to a receive window, where each...
2016/0179591 PUSH INSTRUCTION FOR PUSHING A MESSAGE PAYLOAD FROM A SENDING THREAD TO A RECEIVING THREAD
A processor core of a data processing system receives a push instruction of a sending thread that requests that a message payload identified by at least one...
2016/0179590 ADDRESSING FOR INTER-THREAD PUSH COMMUNICATION
In a data processing system, a switch includes a receive data structure including receive entries each uniquely corresponding to a receive window, where each...
2016/0179589 CENTRALIZED AND DISTRIBUTED NOTIFICATION HANDLING SYSTEM FOR SOFTWARE APPLICATIONS
The present disclosure describes methods, systems, and computer program products for handling notifications. One computer-implemented method includes selecting...
2016/0179588 ANOMALY DETECTION USING A DATA STREAM PROCESSING LANGUAGE FOR ANALYZING INSTRUMENTED SOFTWARE
An instrumentation analysis system processes data streams by executing instructions specified using a data stream language program. The data stream language...
2016/0179587 Scalable Synchronization Mechanism for Distributed Memory
A method comprising receiving control information at a first processing element from a second processing element, synchronizing objects within a shared global...
2016/0179586 LIGHTWEIGHT RESTRICTED TRANSACTIONAL MEMORY FOR SPECULATIVE COMPILER OPTIMIZATION
Embodiments described herein utilize restricted transactional memory (RTM) instructions to implement speculative compile time optimizations that will be...
2016/0179585 METHOD AND APPARATUS FOR WRITE-ONLY INTER-PROCESSOR RESET SYNCHRONIZATION
A method and apparatus is disclosed herein for performing write-only inter processor reset synchronization. In one embodiment, the processing unit comprises: a...
2016/0179584 VIRTUAL SERVICE MIGRATION METHOD FOR ROUTING AND SWITCHING PLATFORM AND SCHEDULER
A virtual service migration method for a routing and switching platform and a scheduler are provided. The virtual service migration method includes: A:...
2016/0179583 EVENT-DRIVEN REOPTIMIZATION OF LOGICALLY-PARTITIONED ENVIRONMENT FOR POWER MANAGEMENT
A method utilizes event-driven reoptimization to reallocate one or more logical partitions within a pool of logically-partitioned data processing systems in a...
2016/0179582 TECHNIQUES TO DYNAMICALLY ALLOCATE RESOURCES FOR LOCAL SERVICE CHAINS OF CONFIGURABLE COMPUTING RESOURCES
Examples may include techniques to provide performance optimizing of service chains to reduce bottlenecks and/or increase efficiency. Information for...
2016/0179581 CONTENT-AWARE TASK ASSIGNMENT IN DISTRIBUTED COMPUTING SYSTEMS USING DE-DUPLICATING CACHE
Systems, devices, and methods are described for performing content-aware task assignment. A resource manager in a distributed computing system can identify...
2016/0179580 RESOURCE MANAGEMENT BASED ON A PROCESS IDENTIFIER
A controller may include circuitry to execute a management policy associated with a computer accessible resource based on a process identifier. The process...
2016/0179579 EFFICIENT VALIDATION OF RESOURCE ACCESS CONSISTENCY FOR A SET OF VIRTUAL DEVICES
Validating access consistency to a set of accessed resources over a set of virtual ports, including determining a number of virtual ports to provision,...
2016/0179578 MULTIPLE STAGE WORKLOAD MANAGEMENT SYSTEM
Provided are techniques for multiple stage workload management. A staging queue and a run queue are provided. A workload is received. In response to...
2016/0179577 Method of Managing the Operation of an Electronic System with a Guaranteed Lifetime
The present disclosure relates to a method of managing the operation of a digital synchronous electronic system with a guaranteed lifetime, using digital...
2016/0179576 QUOTA BASED RESOURCE MANAGEMENT
Embodiments of the present invention provide a quota-based resource management method, computer program product and apparatus for configuring a resource quota...
2016/0179575 ADAPTIVE PARTITIONING FOR OPERATING SYSTEM
An adaptive partition scheduler is a priority-based scheduler that also provides execution time guarantees (fair-share). Execution time guarantees apply to...
2016/0179574 WORK-EFFICIENT, LOAD-BALANCED, MERGE-BASED PARALLELIZED CONSUMPTION OF SEQUENCES OF SEQUENCES
A method, computer readable medium, and system are disclosed for processing a segmented data set. The method includes the steps of receiving a data structure...
2016/0179573 METHOD FOR PROVIDING MAINFRAME STYLE BATCH JOB PROCESSING ON A MODERN COMPUTER SYSTEM
A method is disclosed for controlling a computing apparatus in the execution of a plurality of programs in an ordered fashion, the execution performed in a...
2016/0179572 METHOD AND APPARATUS FOR SELECTING PREEMPTION TECHNIQUE
Provided is a method and apparatus of selecting a preemption technique for a computation unit included in a processor to execute a second task before the at...
2016/0179571 METHOD AND DEVICE FOR SCHEDULING COMMUNICATION SCHEDULABLE UNIT
CSUs belonging to different owners in a radio communication device are scheduled to use multiple processors. The CSUs under different owners can be processed...
2016/0179570 Parallel Computing Without Requiring Antecedent Code Deployment
A method includes identifying a service request including a first and a second computing tasks. The first computing task includes a first program suite having...
2016/0179569 APPARATUS AND METHOD FOR A PROFILER FOR HARDWARE TRANSACTIONAL MEMORY PROGRAMS
An apparatus and method are described for a hardware transactional memory (HTM) profiler. For example, one embodiment of an apparatus comprises a transactional...
2016/0179568 EFFICIENTLY PROVIDING VIRTUAL MACHINE REFERENCE POINTS
Embodiments are directed to establishing efficient virtual machine reference points and to specifying a virtual machine reference point to query incremental...
2016/0179567 Resource Configuration Method of Virtual Machine and Communications Device
A resource configuration method of a virtual machine and a communications device. When an actual requirement of the virtual machine for the network resource is...
2016/0179566 INDEPENDENT ACCESS TO VIRTUAL MACHINE DESKTOP CONTENT
Methods, systems, and techniques for facilitating access to content stored remotely, for example, as part of a virtual machine infrastructure or elsewhere in a...
2016/0179565 Device Remote Access Method, Thin Client, and Virtual Machine
A device remote access method includes receiving, by a bus filter driver on a thin client (TC) side, a request for remote access by a virtual machine (VM) side...
2016/0179564 ISOLATING DATA WITHIN A COMPUTER SYSTEM USING PRIVATE SHADOW MAPPINGS
Virtualization software establishes multiple execution environments within a virtual machine, wherein software modules executing in one environment cannot...
2016/0179563 GENERATING A DEPLOYMENT PATTERN FOR REUSE IN A NETWORKED COMPUTING ENVIRONMENT
An approach for generating a deployment pattern for reuse after the deployment of a set of virtual machines and related application artifacts in a networked...
2016/0179562 RESOURCE CONTROL APPARATUS, METHOD, AND STORAGE MEDIUM
The resource control apparatus according to an embodiment described herein includes an allocating time acquisitor, a usage amount meter, an allocation amount...
2016/0179561 AUTOMATED EXPLOITATION OF VIRTUAL MACHINE RESOURCE MODIFICATIONS
At least one application in a distributed computing environment is deployed. At least one resource of a virtual machine is provided to the at least one...
2016/0179560 CPU Overprovisioning and Cloud Compute Workload Scheduling Mechanism
A method comprising is described. The method includes receiving a virtual machine and a service level objective compute consumption metrics (SLO) parameters...
2016/0179559 INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD
An information processing apparatus includes: a first processing unit that operates in a real environment, performs processing after reading first...
2016/0179558 EXITING MULTIPLE THREADS OF A SIMULATION ENVIRONMENT IN A COMPUTER
Embodiments relate to exiting a multithreaded guest virtual machine (VM) that is running in a simulation environment. An aspect includes executing the...
2016/0179557 EMULATED DEVICE FIRMWARE TESTABLE BY NATIVE OPERATING SYSTEM TOOLS
Firmware is run in an emulated environment such that firmware is not embedded in its designed-for target device. Target device emulation software...
2016/0179556 INPUT/OUTPUT (I/O) DEVICE CONFIGURATION SIGNATURE
A method for building a configuration signature for an input/output (I/O) device is described herein. The configuration signature is built based on descriptors...
2016/0179555 SYSTEM AND METHOD FOR NETWORK-BASED ISCSI BOOT PARAMETER DEPLOYMENT
This disclosure generally relate to remote booting of a computing system. The present technology relates techniques that can enable deploying boot parameters...
2016/0179554 METHODS, SYSTEMS AND APPARATUS TO INITIALIZE A PLATFORM
Methods, apparatus, systems and articles of manufacture are disclosed to initialize a platform. An example disclosed apparatus includes a boot loader manager...
2016/0179553 EXECUTION OF MULTIPLE OPERATING SYSTEMS WITHOUT REBOOTING
Systems and methods for executing multiple operating systems on a computing system without rebooting the computing system are disclosed. Embodiments may...
2016/0179552 INSTRUCTION AND LOGIC FOR A MATRIX SCHEDULER
A processor includes a core and a scheduler. The scheduler includes first and second dependency matrices and a ready determination unit. The scheduler also...
2016/0179551 PIPELINING OUT-OF-ORDER INSTRUCTIONS
Systems, methods and computer program product provide for pipelining out-of-order instructions. Embodiments comprise an instruction reservation station for...
2016/0179550 FAST VECTOR DYNAMIC MEMORY CONFLICT DETECTION
In one embodiment vector conflict detection instructions are disclosed to perform dynamic memory conflict detection within a vectorized iterative scalar...
2016/0179549 Instruction and Logic for Loop Stream Detection
A processor includes a front end including a decoder to decode a branch instruction to perform a branch operation. The processor includes a loop stream unit...
2016/0179548 INSTRUCTION AND LOGIC TO PERFORM AN INVERSE CENTRIFUGE OPERATION
In one embodiment a processing device implements a set of instructions to perform an inverse centrifuge operation using vector or general purpose registers....
2016/0179547 Binary Translation Mechanism
A method is described. The method includes receiving an instruction, accessing a return cache to load a predicted return target address upon determining that...
2016/0179546 TECHNIQUES FOR ENFORCING CONTROL FLOW INTEGRITY USING BINARY TRANSLATION
Various embodiments are generally directed to an apparatus, method and other techniques to determine a valid target address for a branch instruction from...
2016/0179545 INSTRUCTION AND LOGIC FOR REGISTER BASED HARDWARE MEMORY RENAMING
A processor includes a core, a memory subsystem, a predictor module, and a memory rename module. The predictor module may include a first logic to identify a...
2016/0179544 INSTRUCTION AND LOGIC FOR SUPPRESSION OF HARDWARE PREFETCHERS
A processor includes a core, a hardware prefetcher, and a prefetcher control module. The hardware prefetcher includes logic to make speculative prefetch...
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