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Patent # Description
2016/0179543 INSTRUCTION SET ARCHITECTURE WITH OPCODE LOOKUP USING MEMORY ATTRIBUTE
A method decodes instructions based in part on one or more decode-related attributes stored in a memory address translation data structure such as an Effective...
2016/0179542 INSTRUCTION AND LOGIC TO PERFORM A FUSED SINGLE CYCLE INCREMENT-COMPARE-JUMP
In one embodiment a binary translation is used to fuse multiple macroinstructions of an instruction set architecture into a single macroinstruction. Fusible...
2016/0179541 STATELESS CAPTURE OF DATA LINEAR ADDRESSES DURING PRECISE EVENT BASED SAMPLING
A processor includes a logic for stateless capture of data linear addresses (DLA) during precise event based sampling (PEBS) for an out-of-order execution...
2016/0179540 INSTRUCTION AND LOGIC FOR HARDWARE SUPPORT FOR EXECUTION OF CALCULATIONS
A processor includes a front end with a decoder with logic to identify a calculation instruction associated with a vector read. The processor also includes an...
2016/0179539 INSTRUCTION AND LOGIC TO PERFORM A CENTRIFUGE OPERATION
A processing device implements a set of instructions to perform a centrifuge operation using vector or general purpose registers. In one embodiment, the...
2016/0179538 METHOD AND APPARATUS FOR IMPLEMENTING AND MAINTAINING A STACK OF PREDICATE VALUES WITH STACK SYNCHRONIZATION...
Embodiments of a method and apparatus for implementing and maintaining a stack of predicate values with stack synchronization instructions. In one embodiment...
2016/0179537 METHOD AND APPARATUS FOR PERFORMING REDUCTION OPERATIONS ON A SET OF VECTOR ELEMENTS
An apparatus and method are described for performing SIMD reduction operations. For example, one embodiment of a processor comprises: a value vector register...
2016/0179536 Early termination of segment monitoring in run-time code parallelization
A processor includes a processing pipeline including multiple hardware threads and configured to execute software code instructions that are stored in a...
2016/0179535 METHOD AND APPARATUS FOR EFFICIENT EXECUTION OF NESTED BRANCHES ON A GRAPHICS PROCESSOR UNIT
An apparatus and method for executing nested control flow instructions on a graphics processing unit (GPU). For example, one embodiment of a processor...
2016/0179534 INSTRUCTION LENGTH DECODING
A processor includes a binary translator an a decoder. The binary translator includes logic to analyze a stream of atomic instructions, identify words by...
2016/0179533 SCALABLE EVENT HANDLING IN MULTI-THREADED PROCESSOR CORES
In one embodiment, a processor includes a frontend unit having an instruction decoder to receive and to decode instructions of a plurality of threads, an...
2016/0179532 MANAGING ALLOCATION OF PHYSICAL REGISTERS IN A BLOCK-BASED INSTRUCTION SET ARCHITECTURE (ISA), AND RELATED...
Managing allocation of physical registers in a block-based instruction set architecture (ISA), and related apparatuses and methods, are disclosed. In one...
2016/0179531 COMPILER METHOD FOR GENERATING INSTRUCTIONS FOR VECTOR OPERATIONS IN A MULTI-ENDIAN INSTRUCTION SET
A compiler includes a vector instruction processing mechanism that generates instructions for vector instructions in a way that assures correct operation in a...
2016/0179530 INSTRUCTION AND LOGIC TO PERFORM A VECTOR SATURATED DOUBLEWORD/QUADWORD ADD
In several embodiments, vector extensions to an instruction set architecture include instructions to perform saturated signed and unsigned integer additions....
2016/0179529 METHOD AND APPARATUS FOR PERFORMING A VECTOR BIT REVERSAL AND CROSSING
An apparatus and method for performing a vector bit reversal and crossing. For example, one embodiment of a processor comprises: a first source vector register...
2016/0179528 METHOD AND APPARATUS FOR PERFORMING CONFLICT DETECTION
An apparatus and method are described for performing conflict detection operations. For example, one embodiment of a processor comprises: a first source vector...
2016/0179527 METHOD AND APPARATUS FOR EFFICIENTLY MANAGING ARCHITECTURAL REGISTER STATE OF A PROCESSOR
An apparatus and method for efficiently managing the architectural state of a processor. For example, one embodiment of a processor comprises: a source mask...
2016/0179526 METHOD AND APPARATUS FOR VECTOR INDEX LOAD AND STORE
An apparatus and method for performing vector index loads and stores. For example, one embodiment of a processor comprises: a vector index register to store a...
2016/0179525 COMPILER METHOD FOR GENERATING INSTRUCTIONS FOR VECTOR OPERATIONS IN A MULTI-ENDIAN INSTRUCTION SET
A compiler includes a vector instruction processing mechanism that generates instructions for vector instructions in a way that assures correct operation in a...
2016/0179524 COMPILER METHOD FOR GENERATING INSTRUCTIONS FOR VECTOR OPERATIONS ON A MULTI-ENDIAN PROCESSOR
A compiler includes a vector instruction processing mechanism that generates instructions for vector instructions in a way that assures correct operation in a...
2016/0179523 APPARATUS AND METHOD FOR VECTOR BROADCAST AND XORAND LOGICAL INSTRUCTION
An apparatus and method are described for performing a vector broadcast and XORAND logical instruction. For example, one embodiment of a processor comprises:...
2016/0179522 METHOD AND APPARATUS FOR PERFORMING A VECTOR BIT REVERSAL
An apparatus and method for performing a vector bit reversal. For example, one embodiment of a processor comprises: a source vector register to store a...
2016/0179521 METHOD AND APPARATUS FOR EXPANDING A MASK TO A VECTOR OF MASK VALUES
An apparatus and method for performing a mask expand. For example, one embodiment of a processor comprises: a source mask register to store a plurality of mask...
2016/0179520 METHOD AND APPARATUS FOR VARIABLY EXPANDING BETWEEN MASK AND VECTOR REGISTERS
An apparatus and method for performing a variable mask-vector expand. For example, one embodiment of a processor comprises: a source mask register to store a...
2016/0179519 Multi-Phased and Multi-Threaded Program Execution Based on SIMD Ratio
A microprocessor is configured to execute programs divided into discrete phases. A scheduler is provided for scheduling instructions. A plurality of resources...
2016/0179518 NON-SERIALIZED PUSH INSTRUCTION FOR PUSHING A MESSAGE PAYLOAD FROM A SENDING THREAD TO A RECEIVING THREAD
In at least some embodiments, a processor core executes a sending thread including a first push instruction and a second push instruction subsequent to the...
2016/0179517 NON-SERIALIZED PUSH INSTRUCTION FOR PUSHING A MESSAGE PAYLOAD FROM A SENDING THREAD TO A RECEIVING THREAD
In at least some embodiments, a processor core executes a sending thread including a first push instruction and a second push instruction subsequent to the...
2016/0179516 INFORMATION PROCESSING DEVICE AND CONTROL METHOD
An information processing device includes: an arithmetic processing device including a plurality of arithmetic processing units and a memory, wherein the...
2016/0179515 APPARATUS AND METHOD FOR PERFORMING A CHECK TO OPTIMIZE INSTRUCTION FLOW
An apparatus and method for performing a check on inputs to a mathematical instruction and selecting a default sequence efficiently managing the architectural...
2016/0179514 INSTRUCTION AND LOGIC FOR SHIFT-SUM MULTIPLIER
A processor includes a front end including a decoder, an execution unit including a shift-sum multiplier (SSM), and a retirement unit. The decoder includes...
2016/0179513 SERVER-SIDE TRANSLATION FOR CUSTOM APPLICATION SUPPORT IN CLIENT-SIDE SCRIPTS
Embodiments of the present invention address deficiencies of the art in respect to server-side processing and provide a novel and non-obvious method, system...
2016/0179512 IDENTIFYING EQUIVALENT JAVASCRIPT EVENTS
Identifying equivalent JavaScript events includes receiving source code containing two JavaScript events for equivalency analysis, extracting an HTML element...
2016/0179511 PARALLEL DEVELOPMENT OF A SOFTWARE SYSTEM
Parallel development of a software system having multiple streams is managed. A selected section from a first artifact in a first stream of the multiple...
2016/0179510 PARALLEL DEVELOPMENT OF A SOFTWARE SYSTEM
Parallel development of a software system having multiple streams is managed. A selected section from a first artifact in a first stream of the multiple...
2016/0179509 CONTAINER BASED APPLICATION REIFICATION
Embodiments disclosed herein provide systems, methods, and computer readable media for container based application reification. In a particular embodiment, an...
2016/0179508 ASSERTIONS BASED ON RECENTLY CHANGED CODE
The present disclosure relates to managing assertions in program source code in an integrated development environment (IDE) tool. According to one embodiment,...
2016/0179507 ASSERTIONS BASED ON RECENTLY CHANGED CODE
The present disclosure relates to managing assertions in program source code in an integrated development environment (IDE) tool. According to one embodiment,...
2016/0179506 INCREASING PROFICIENCY STATUS OF DEVELOPERS
The present disclosure relates to a tool for increasing efficiency of development and upskilling of developers of software. The system may be configured to...
2016/0179505 SYSTEMS AND METHODS FOR ENFORCING CODE REVIEWS
Techniques for enforcing software reviews are described. For example, a machine receives a commit request to commit code to a repository. The machine, in...
2016/0179504 REFACTORING DATA FLOW APPLICATIONS WITHOUT SOURCE CODE CHANGES OR RECOMPILATION
Systems and methods may provide refactoring data flow applications without source code changes or recompilation. An apparatus may create a map file that...
2016/0179503 OPTIMIZING PROGRAM PERFORMANCE WITH ASSERTION MANAGEMENT
The present disclosure relates to maintaining assertions in source code components of a development project by an integrated development environment (IDE)...
2016/0179502 IDENTIFYING SOURCE CODE USED TO BUILD EXECUTABLE FILES
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for identifying source code used to build executable. One of...
2016/0179501 CALCULATING CONFIDENCE VALUES FOR SOURCE CODE BASED ON AVAILABILITY OF EXPERTS
Software that uses machine logic to identify expert(s) for functional components of source code, determining a confidence value for each functional component...
2016/0179500 FIRMWARE VARIABLE UPDATE METHOD
A firmware variable update method for BIOS of a computer system is provided. The firmware variable update method includes writing an update capsule file and a...
2016/0179499 SYSTEM AND METHOD FOR CLOUD PROVISIONING AND APPLICATION DEPLOYMENT
Embodiments described herein provide systems and methods for installing or otherwise supporting applications in a cloud environment and systems and methods for...
2016/0179498 APP STORE UPDATE NOTIFICATION AND WARNING SYSTEM
A system for maintaining and upgrading hardware device functioning provides processes to select and install updates for software (e.g., applications or apps)...
2016/0179497 Zero Downtime Upgrade of Database Applications Using Triggers and Calculated Fields
An upgrade of a first version of a database application to a second version of a database application that both have a same data schema is initiated. The first...
2016/0179496 Delivery of Correction Packages
A system, a method, and a computer-program product for delivering of correction packages are disclosed. At least one correction instruction is generated based...
2016/0179495 Device and method for packaging application
An application packaging device and method are provided. The method includes: an installation package of an application is unzipped; each piece of channel...
2016/0179494 INTEGRATION OF AN ARBITRARY SERVER INSTALLED AS AN EXTENSION OF A COMPUTING PLATFORM
A package including a native monitoring library and a shared memory API interface to the native monitoring library is integrated into an arbitrary server to...
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