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Patent # Description
2016/0190320 SURFACE TENSION MODIFICATION USING SILANE WITH HYDROPHOBIC FUNCTIONAL GROUP FOR THIN FILM DEPOSITION
A semiconductor structure that includes crystalline surfaces and amorphous hydrophilic surfaces is provided. The hydrophilic surfaces are treated with silane...
2016/0190319 Non-Planar Semiconductor Devices having Multi-Layered Compliant Substrates
Non-planar semiconductor devices having multi-layered compliant substrates and methods of fabricating such non-planar semiconductor devices are described. For...
2016/0190318 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a substrate, first strain-inducing source and drain structures, a first gate structure, a first channel region, second...
2016/0190317 HETERO-CHANNEL FINFET
A hetero-channel FinFET device provides enhanced switching performance over a FinFET device having a silicon channel, and is easier to integrate into a...
2016/0190316 CHARGE CARRIER TRANSPORT FACILITATED BY STRAIN
A semiconductor structure and formation thereof. The semiconductor structure has a first semiconductor layer with a first lattice structure and a second...
2016/0190315 METHOD AND STRUCTURE OF MAKING ENHANCED UTBB FDSOI DEVICES
An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of...
2016/0190314 VERTICAL SLIT TRANSISTOR WITH OPTIMIZED AC PERFORMANCE
A vertical slit transistor includes raised source, drain, and channel regions in a semiconductor substrate. Two gate electrodes are positioned adjacent...
2016/0190313 LOCAL BURIED CHANNEL DIELECTRIC FOR VERTICAL NAND PERFORMANCE ENHANCEMENT AND VERTICAL SCALING
A non-volatile memory device and a method for forming the non-volatile memory device are disclosed. The memory device utilizes a local buried channel...
2016/0190312 VERTICAL GATE ALL-AROUND TRANSISTOR
Vertical GAA FET structures are disclosed in which a current-carrying nanowire is oriented substantially perpendicular to the surface of a silicon substrate....
2016/0190311 SEMICONDUCTOR DEVICE
A semiconductor device according to the present invention includes: an insulating layer; a semiconductor layer of a first conductive type laminated on the...
2016/0190310 RADIO FREQUENCY LDMOS DEVICE AND A FABRICATION METHOD THEREFOR
A radio frequency LDMOS device, wherein the drift region includes a first injection region and a second injection region; the first injection region situated...
2016/0190309 NANO MOSFET WITH TRENCH BOTTOM OXIDE SHIELDED AND THIRD DIMENSIONAL P-BODY CONTACT
A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each...
2016/0190308 SILICON-CARBIDE TRENCH GATE MOSFETS
In a general aspect, an apparatus can include a semiconductor substrate, a drift region disposed in the semiconductor substrate; a body region disposed in the...
2016/0190307 SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SAME
A silicon carbide semiconductor device includes a drift layer of a first conductivity type, a source region of the first conductivity type, an active trench...
2016/0190306 FINFET DEVICE WITH A SUBSTANTIALLY SELF-ALIGNED ISOLATION REGION POSITIONED UNDER THE CHANNEL REGION
One illustrative device disclosed herein includes, among other things, a semiconductor substrate, a fin structure, a gate structure positioned around a portion...
2016/0190305 Structure and Method for 3D FinFET Metal Gate
The present disclosure provides a semiconductor structure in accordance with some embodiments. The semiconductor structure includes a semiconductor substrate;...
2016/0190304 DEFECT-FREE STRAIN RELAXED BUFFER LAYER
A modified silicon substrate having a substantially defect-free strain relaxed buffer layer of SiGe is suitable for use as a foundation on which to construct a...
2016/0190303 SILICON GERMANIUM-ON-INSULATOR FINFET
A method of making a structurally stable SiGe-on-insulator FinFET employs a silicon nitride liner to prevent de-stabilizing oxidation at the base of a SiGe...
2016/0190302 SOI BASED FINFET WITH STRAINED SOURCE-DRAIN REGIONS
A method of fabricating a semiconductor device where: (i) the fins are formed over a porous semiconductor material layer (for example, a silicon layer); and...
2016/0190301 Semiconductor Device with Stripe-Shaped Trench Gate Structures, Transistor Mesas and Diode Mesas
A semiconductor device includes stripe-shaped trench gate structures that extend in a semiconductor body along a first horizontal direction. Transistor mesas...
2016/0190300 SILICON CARBIDE (SiC) DEVICE WITH IMPROVED GATE DIELECTRIC SHIELDING
In one general aspect, an apparatus can include a silicon carbide (SiC) device can include a gate dielectric, a first doped region having a first conductivity...
2016/0190299 SEMICONDUCTOR DEVICE HAVING VIA HOLE COATED IN SIDE SURFACES WITH HEAT TREATED NITRIDE METAL AND METHOD TO FORM...
A semiconductor device having a via hole whose side surface is covered with nitride metals is disclosed. The via hole is formed within an insulating region...
2016/0190298 FORMING ENHANCEMENT MODE III-NITRIDE DEVICES
A method of fabricating a III-N device includes forming a III-N channel layer on a substrate, a III-N barrier layer on the channel layer, an insulator layer on...
2016/0190297 HIGH-ELECTRON-MOBILITY TRANSISTORS
High-electron-mobility transistors that include field plates are described. In a first implementation, a HEMT includes a first and a second semiconductor...
2016/0190296 GALLIUM NITRIDE BASED HIGH ELECTRON MOBILITY TRANSISTOR INCLUDING AN ALUMINUM GALLIUM NITRIDE BARRIER LAYER
A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is...
2016/0190295 FIELD EFFECT TRANSISTOR
A field effect transistor includes a substrate; a first semiconductor layer, disposed over the substrate; a second semiconductor layer, disposed over the first...
2016/0190294 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
In order to improve the characteristics of a semiconductor device including: a channel layer and a barrier layer formed above a substrate; and a gate electrode...
2016/0190293 A Transistor and Method of Making
A SiGe HBT has an inverted heterojunction structure, where the emitter layer is formed prior to the base layer and the collector layer. The frequency...
2016/0190292 BIPOLAR TRANSISTOR WITH EXTRINSIC BASE REGION AND METHODS OF FABRICATION
The present disclosure relates to integrated circuit (IC) structures and methods of forming the same. An IC structure according to the present disclosure can...
2016/0190291 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
A transistor with superior electric characteristics is manufactured. An oxide insulating film is formed over a substrate, an oxide semiconductor film is formed...
2016/0190290 ATOMIC LAYER DEPOSITION OF P-TYPE OXIDE SEMICONDUCTOR THIN FILMS
Provided herein are methods of depositing p-type metal oxide thin films by atomic layer deposition (ALD). Also provided are p-type metal oxide thin films and...
2016/0190289 METHODS OF FORMING TRANSISTOR STRUCTURES
Methods for fabricating transistor structures are provided, the methods including: forming a fin structure with an upper fin portion and a lower fin portion,...
2016/0190288 ENRICHED, HIGH MOBILITY STRAINED FIN HAVING BOTTOM DIELECTRIC ISOLATION
Embodiments are directed to a method of enriching and electrically isolating a fin of a FinFET. The method includes forming at least one fin. The method...
2016/0190287 METHOD FOR FORMING SEMICONDUCTOR DEVICE
A method of forming a semiconductor device includes following steps. Firstly, a substrate having a transistor is provided, where the transistor includes a...
2016/0190286 SURFACE PASSIVATION FOR GERMANIUM-BASED SEMICONDUCTOR STRUCTURE
The present disclosure provides a method forming a semiconductor device in accordance with some embodiments. The method includes receiving a substrate having a...
2016/0190285 ENRICHED, HIGH MOBILITY STRAINED FIN HAVING BOTTOM DIELECTRIC ISOLATION
Embodiments are directed to a method of enriching and electrically isolating a fin of a FinFET. The method includes forming at least one fin. The method...
2016/0190284 METHOD FOR FABRICATING LIGHTLY DOPED DRAIN AREA, THIN FILM TRANSISTOR AND ARRAY SUBSTRATE
Embodiments of the disclosure provide a method for fabricating a lightly doped drain area, a thin film transistor, and a thin film transistor array substrate....
2016/0190283 FABRICATION OF MOSFET DEVICE WITH REDUCED BREAKDOWN VOLTAGE
Fabricating a semiconductor device comprises: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the...
2016/0190282 VERTICAL TRANSISTOR DEVICES FOR EMBEDDED MEMORY AND LOGIC TECHNOLOGIES
Vertical transistor devices are described. For example, in one embodiment, a vertical transistor device includes an epitaxial source semiconductor region...
2016/0190281 EXTENDED-DRAIN TRANSISTOR USING INNER SPACER
An MOS device with increased drain-source voltage (Vds) includes a source region and a drain region deposited on a substrate. A gate region includes an inner...
2016/0190280 STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE WITH GATE STACK
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a...
2016/0190279 Unknown
A SOI substrate is covered by a semiconductor material pattern which comprises a dividing pattern made from electrically insulating material. The dividing...
2016/0190278 COMPOUND SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A compound semiconductor device includes: an electron transit layer; an electron supply layer formed over the electron transit layer; and a GaN cap layer...
2016/0190277 BIPOLAR TRANSISTOR STRUCTURE AND A METHOD OF MANUFACTURING A BIPOLAR TRANSISTOR STRUCTURE
According to various embodiments, a bipolar transistor structure may include: a substrate; a collector region in the substrate; a base region disposed over the...
2016/0190276 METHOD AND SYSTEM FOR IN-SITU ETCH AND REGROWTH IN GALLIUM NITRIDE BASED DEVICES
A method of regrowing material includes providing a III-nitride structure including a masking layer and patterning the masking layer to form an etch mask. The...
2016/0190275 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
It is made possible to provide a method for manufacturing a semiconductor device that has a high-quality insulating film in which defects are not easily...
2016/0190274 METHODS OF FORMING CONTACT STRUCTURES FOR SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES
A device includes a first epi semiconductor material positioned in a source/drain region of the device, the first epi semiconductor material having a first...
2016/0190273 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
The reliability of a semiconductor device is increased by suppression of a variation in electric characteristics of a transistor as much as possible. As a...
2016/0190272 METHOD OF FORMING HORIZONTAL GATE ALL AROUND STRUCTURE
This disclosure provides a horizontal structure by using a double STI recess method. The double STI recess method includes: forming a plurality of fins on the...
2016/0190271 SEMICONDUCTOR DEVICE HAVING FILLER AND METHOD OF MANUFACTURING THE SAME
A semiconductor device and a method of manufacturing a semiconductor device, the device including an active fin protruding from a substrate and extending in a...
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