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Patent # Description
2016/0190070 Multiple Edge Enabled Patterning
Provided is an alignment mark having a plurality of sub-resolution elements. The sub-resolution elements each have a dimension that is less than a minimum...
2016/0190069 METHOD FOR FORMING IDENTIFICATION MARKS ON REFRACTORY MATERIAL SINGLE CRYSTAL SUBSTRATE, AND REFRACTORY...
An identification mark formation method for forming an identification mark on a refractory material single crystal substrate that is made of one selected from...
2016/0190068 CONTACT STRUCTURE AND FORMATION THEREOF
A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the...
2016/0190067 SEMICONDUCTOR STRUCTURES WITH ISOLATED OHMIC TRENCHES AND STAND-ALONE ISOLATION TRENCHES AND RELATED METHOD
A method of forming a semiconductor structure in a semiconductor-on-insulator (SOI) substrate and semiconductor structure so formed are provided. The SOI...
2016/0190066 THROUGH SILICON VIAS
A device and methods for forming a device are disclosed. A substrate is provided and a TSV is formed in the substrate through a top surface of the substrate....
2016/0190065 INTERCONNECT STRUCTURE WITH MISALIGNED METAL LINES COUPLED USING DIFFERENT INTERCONNECT LAYER
In some embodiments, an interconnect structure includes a first metal line, a second metal line and a first connection structure. The first metal line is...
2016/0190064 SEMICONDUCTOR DEVICE WITH SELF-PROTECTING FUSE AND METHOD OF FABRICATING THE SAME
A semiconductor device with the metal fuse is provided. The metal fuse connects an electronic component (e.g., a transistor) and a existing dummy feature which...
2016/0190063 CHIP PACKAGE AND FABRICATION METHOD THEREOF
A chip package included a chip, a first though hole, a laser stop structure, a first isolation layer, a second though hole and a conductive layer. The first...
2016/0190062 INTERCONNECTION STRUCTURE AND MANUFACTURING METHOD THEREOF
An interconnection structure includes a first dielectric layer, a first conductor, an etch stop layer, a second dielectric layer, and a second conductor. The...
2016/0190061 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Provided is a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate and a dielectric layer. The dielectric...
2016/0190060 FORMING LAYERS OF MATERIALS OVER SMALL REGIONS BY SELECTIV CHEMICAL REACTION INCLUDING LIMITING ENCHROACHMENT...
A method of an aspect includes forming a first thicker layer of a first material over a first region having a first surface material by separately forming each...
2016/0190059 PACKAGE APPARATUS AND MANUFACTURING METHOD THEREOF
A package apparatus comprises a first conductive wiring layer, a first conductive pillar layer, a first conductive glue layer, an internal component, a second...
2016/0190058 Semiconductor Device
The semiconductor device includes a wiring substrate having a plurality of ball lands formed on a lower surface of a core layer, a solder resist film covering...
2016/0190057 INTERCONNECT STRUCTURE FOR MOLDED IC PACKAGES
Various examples are provided for interconnection structures for molded IC packages. In one example, among others, an IC package includes a substrate and an...
2016/0190056 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE MECHANISM AND METHOD OF MANUFACTURE THEREOF
An integrated circuit packaging system, and a method of manufacture thereof, including: a substrate; a metal core interconnect attached to the substrate; an...
2016/0190055 FUNCTIONAL PANEL, LIGHT-EMITTING PANEL, DISPLAY PANEL, AND SENSOR PANEL
A functional panel is provided. The functional panel includes a first substrate, a second substrate, a bonding layer, a functional element, a protective layer,...
2016/0190054 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER SUPPORT STRUCTURE MECHANISM AND METHOD OF MANUFACTURE THEREOF
A system and method of manufacture of an integrated circuit packaging system includes: a base substrate, the base substrate includes a base terminal; an...
2016/0190053 WIRING SUBSTRATE
A wiring substrate includes a first substrate and an electronic component mounted on an upper surface of the first substrate. A first pad is formed on an...
2016/0190052 FEEDTHROUGH ASSEMBLIES AND METHODS OF FORMING SAME
Various embodiments of a feedthrough assembly and methods of forming such assemblies are disclosed. In one or more embodiments, the feedthrough assembly can...
2016/0190051 Electronic device
An electronic device, suitable for achieving a smaller size, includes a semiconductor substrate having a main surface and a back surface opposite to the main...
2016/0190050 METHOD FOR MANUFACTURING AN INTERPOSER, INTERPOSER AND CHIP PACKAGE STRUCTURE
A method for manufacturing an interposer includes the following steps. Conductive beads is filled in a blind via of a substrate and a solder layer of each...
2016/0190049 SEMICONDUCTOR DEVICE
To improve noise immunity of a semiconductor device. A wiring substrate of a semiconductor device includes a first wiring layer where a wire is formed to which...
2016/0190048 STACKED CHIP-ON-BOARD MODULE WITH EDGE CONNECTOR
A module can include a module card and first and second microelectronic elements having front surfaces facing a first surface of the module card. The module...
2016/0190047 ELECTRONIC DEVICE HAVING A LEAD WITH SELECTIVELY MODIFIED ELECTRICAL PROPERTIES
A die package having a plurality of connection pads, a die substrate supporting a plurality of connection elements, a first lead having a first metal core with...
2016/0190046 PROCESS FOR MANUFACTURING A PACKAGE FOR A SURFACE-MOUNT SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
A surface-mount electronic device includes a body of semiconductor material, and a lead frame that includes a plurality of contact terminals. The plurality of...
2016/0190045 SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME
A semiconductor device includes: a semiconductor element having a functional surface formed with a functional circuit and a reverse surface opposite to the...
2016/0190044 CHIP PACKAGE AND A WAFER LEVEL PACKAGE
Various embodiments provide for a chip package consisting of a layer over a carrier, further carrier material over the layer, wherein one or more portions of...
2016/0190043 Electronic Devices and Methods of Manufacturing Electronic Devices
Disclosed are a foldable and spreadable electronic device and a method of manufacturing the electronic device. The electronic device may include a flexible...
2016/0190042 DEVICES, SYSTEMS AND METHODS FOR MANUFACTURING THROUGH-SUBSTRATE VIAS AND FRONT-SIDE STRUCTURES
Methods of manufacturing semiconductor devices and semiconductor devices with through-substrate vias (TSVs). One embodiment of a method of manufacturing a...
2016/0190041 DEVICE WITHOUT ZERO MARK LAYER
Devices and methods for forming a device are disclosed. The method includes providing a substrate having first and second surfaces. At least one through...
2016/0190040 WIRING LAYER FORMING METHOD, WIRING LAYER FORMING SYSTEM AND RECORDING MEDIUM
A seed layer and a barrier layer located outside a wiring layer on a surface of a substrate are easily removed by an etching process. A metal layer 25 composed...
2016/0190039 SUBSTRATE STRUCTURE
A substrate structure includes: a substrate body defined with a layout area, a sealing member and a cutting area, the sealing member being adjacent to the...
2016/0190038 COOLER AND SEMICONDUCTOR DEVICE HAVING COOLER
A cooler for cooling a semiconductor module includes a top plate; a jacket having a side plate and a bottom plate and firmly fixed to the top plate; a...
2016/0190037 HEAT SPREADER WITH HIGH HEAT FLUX AND HIGH THERMAL CONDUCTIVITY
A system and method is disclosed for fabricating a heat spreader system, including providing a plurality of bottom microporous wicks recessed in a bottom...
2016/0190036 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor element having a front surface and a rear surface, a pair of heat sinks disposed facing each other so as to...
2016/0190035 THERMAL INTERFACE MATERIAL LAYER AND PACKAGE-ON-PACKAGE DEVICE INCLUDING THE SAME
Provided are a thermal interface material layer and a package-on-package device including the same. The package-on-package device may include a thermal...
2016/0190034 POWER CONVERSION DEVICE
A power conversion device includes a heat releasing heatsink, a printed circuit board provided on the heatsink and having a through hole and wires, a metal...
2016/0190033 SEMICONDUCTOR MODULE UNIT AND SEMICONDUCTOR MODULE
A semiconductor module includes a semiconductor chip; an insulating circuit board that has on one of principal surfaces of an insulating substrate a circuit...
2016/0190032 WIRING BOARD AND SEMICONDUCTOR PACKAGE INCLUDING WIRING BOARD
According to an embodiment, a wiring board includes an insulating board including a heat transfer region made of silicon nitride and having a thickness in a...
2016/0190031 SEMICONDUCTOR PACKAGE WITH CANTILEVER PADS
One or more embodiments are directed to semiconductor packages with one or more cantilever pads. In one embodiment a recess is located in a substrate of the...
2016/0190030 SELF-LIMITING CHEMICAL VAPOR DEPOSITION AND ATOMIC LAYER DEPOSITION METHODS
Methods for depositing silicon on a semiconductor or metallic surface include cycling dosing of silane and chlorosilane precursors at a temperature between...
2016/0190029 METHOD OF MAKING AN ELECTRONIC DEVICE INCLUDING TWO-STEP ENCAPSULATION AND RELATED DEVICES
A method of making an electronic device may include positioning an integrated circuit (IC) die on an upper surface of a grid array substrate having connections...
2016/0190028 METHOD AND STRUCTURE FOR FAN-OUT WAFER LEVEL PACKAGING
A method for fan-out wafer level packaging includes: providing a carrier substrate; forming a strippable protective film with a polarity of openings; forming...
2016/0190027 METHODS OF FORMING PANEL EMBEDDED DIE STRUCTURES
Methods of forming molded panel coreless package structures are described. Those methods and structures may include fabrication of embedded die packages using...
2016/0190026 GLASS COMPOSITION FOR PROTECTING SEMICONDUCTOR JUNCTION, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND...
Provided is a glass composition for protecting a semiconductor junction which contains at least SiC.sub.2, B.sub.2O.sub.3, Al.sub.2O.sub.3, ZnO and at least...
2016/0190025 ELECTRICAL SWITCH AND MOUNTING ASSEMBLY THEREFOR`
A mounting assembly is for an electrical switch, such as for example, a dimmer switch, which includes a heat sink. The mounting assembly includes a switching...
2016/0190024 SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD AND RECORDING MEDIUM RECORDING SUBSTRATE PROCESSING...
A substrate processing apparatus includes at least one process module configured to process first substrates. A position detector is configured to detect first...
2016/0190023 WAFER BACK-SIDE POLISHING SYSTEM AND METHOD FOR INTEGRATED CIRCUIT DEVICE MANUFACTURING PROCESSES
A wafer polishing process includes polishing a central area on the back side of a wafer, polishing a peripheral area on the back side of the wafer, buffing the...
2016/0190022 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
Degradation of reliability of a semiconductor device is prevented. An electrode pad included mainly of aluminum is formed over a main surface of a...
2016/0190021 INTEGRATED CIRCUITS, METHODS OF FORMING THE SAME, AND METHODS OF DETERMINING GATE DIELECTRIC LAYER ELECTRICAL...
Integrated circuits, methods of forming integrated circuits, and methods of determining gate dielectric layer electrical thickness in integrated circuits are...
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