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Patent # Description
2016/0188519 METHOD, APPARATUS, SYSTEM FOR EMBEDDED STREAM LANES IN A HIGH-PERFORMANCE INTERCONNECT
In an example, a high-performance interconnect (HPI) is provisioned without a separate stream lane. To provide equivalent functionality, stream lane data are...
2016/0188518 Opaque Bridge for Peripheral Component Interconnect Express Bus Systems
A host system may couple to a PCIe subsystem. During setup of the PCIe subsystem, the BIOS in the host system may first be informed that the devices to be...
2016/0188517 ENCAPSULATION ENABLED PCIE VIRTUALISATION
There is herein described a method for transmitting data packets from a first device through a switch to a second device. The method is performed at an...
2016/0188516 PASS-THROUGH CONVERGED NETWORK ADAPTOR (CNA) USING EXISTING ETHERNET SWITCHING DEVICE
According to one embodiment, a method includes performing functionality of a management plane and a control plane for a switch system using a processor of an...
2016/0188515 METHOD AND APPARATUS FOR GROUPING MULTIPLE SAS EXPANDERS TO FORM A SINGLE COHESIVE SAS EXPANDER
A SAS (Serial Attached SCSI or Serial Attached Small Computer System Interface) switch includes a master SAS expander and a multitude of slave expanders...
2016/0188514 CIRCUIT AND METHOD FOR INTERFACING UNIVERSAL SERIAL BUS
USB controllers, systems and methods are presented to conserve power in a USB controller, in which a transmitter transmits data to a line of a connected USB...
2016/0188513 Intelligent Network Fabric to Connect Multiple Computer Nodes with One or More SR-IOV Devices
This disclosure pertains to an intelligent network fabric used to connect multiple computer nodes with one or more SR-IOV devices. The intelligent fabric...
2016/0188512 ELECTRONIC DEVICE COUPLING SYSTEM AND METHOD
An electronic device coupling system includes a master electronic device and a plurality of slave electronic devices. The master electronic device includes a...
2016/0188511 COMPUTER SYSTEM AND COUPLING CONFIGURATION CONTROL METHOD
A computer system includes a switch having a plurality of ports, a plurality of devices coupled to the plurality of ports, and a management system coupled to...
2016/0188510 METHOD FETCHING/PROCESSING NVMe COMMANDS IN MULTI-PORT, SR-IOV OR MR-IOV SUPPORTED PCIe BASED STORAGE DEVICES
A method of fetching I/O commands received from a host in a Peripheral Component Interconnect Express (PCIe) device includes; assigning priority to PCIe...
2016/0188509 METHOD FOR AUTOMATICALLY MATCHING ELECTRONIC DEVICES
A method for group matching electronic devices includes entering a system for group matching, activating an automatic group matching mode of a master...
2016/0188508 MULTIPLEX MODULE AND ELECTRONIC APPARATUS THEREOF FOR HIGH-SPEED SERIAL TRANSMISSION
A multiplex module for high-speed serial transmission is provided. The multiplex module has at least one external connection terminal and at least one circuit...
2016/0188507 ELECTRONIC DEVICE GROUP-COUPLING SYSTEM AND METHOD
An electronic device coupling system includes a master electronic device and a plurality of slave electronic devices which are each independently connected to...
2016/0188506 TRANSCEIVER MULTIPLEXING OVER USB TYPE-C INTERCONNECTS
An apparatus for transceiver multiplexing over USB Type-C interconnects is described herein. The apparatus includes a processor, a memory, a USB Type-C...
2016/0188505 DIRECT ACCESS TO A HARDWARE DEVICE FOR VIRTUAL MACHINES OF A VIRTUALIZED COMPUTER SYSTEM
In a virtualized computer system in which a guest operating system runs on a virtual machine of a virtualized computer system, a computer-implemented method of...
2016/0188504 POSTING INTERRUPTS TO VIRTUAL PROCESSORS
Embodiments of systems, apparatuses, and methods for posting interrupts to virtual processors are disclosed. In one embodiment, an apparatus includes look-up...
2016/0188503 VIRTUAL LEGACY WIRE
In an example, a system on chip (SoC) includes virtual legacy wire (VLW) functionality. The VLW signal virtualizes a physical interrupt existing in legacy...
2016/0188502 Ring Bus Architecture for Use in a Memory Module
Ring bus architectures for use in a memory module are disclosed. A memory module may include a ring bus controller and a bus bridge positioned on a primary...
2016/0188501 Reordering Responses in a High Performance On-Chip Network
Flow logic supports concurrency of multiple threads and/or tag IDs to be concurrently communicated across the interconnect while allowing the one or more...
2016/0188500 PACKED WRITE COMPLETIONS
A plurality of completed writes to memory are identified corresponding to a plurality of write requests from a host device received over a buffered memory...
2016/0188499 TIGHTLY-COUPLED DISTRIBUTED UNCORE COHERENT FABRIC
Selected portions of an uncore fabric of a system-on-a-chip (SoC) or other embedded system are divided into two independent pipelines. Each pipeline operates...
2016/0188498 Memory System Topologies Including A Buffer Device And An Integrated Circuit Memory Device
Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled...
2016/0188497 ELECTRONIC DEVICE WITH INTEGRATION FUNCTION AND MULTIPLE DEVICES INTEGRATING CONTROL METHOD
A multiple device integrating control method, includes: detecting whether a first connection port of an electronic device is connected to a first device;...
2016/0188496 COMPUTER INSTRUCTIONS FOR LIMITING ACCESS VIOLATION REPORTING WHEN ACCESSING STRINGS AND SIMILAR DATA STRUCTURES
Embodiments are directed to a computer implemented method of accessing a data frame, wherein a first portion of the data frame is in a first memory block, and...
2016/0188495 EVENT TRIGGERED ERASURE FOR DATA SECURITY
One aspect of the present description provides for automatically erasing at least a portion of a memory such as a nonvolatile memory, for example, of a device...
2016/0188494 CACHE STRUCTURE FOR A COMPUTER SYSTEM PROVIDING SUPPORT FOR SECURE OBJECTS
A method that protects a confidentiality and an integrity of information in a secure object from other software on the system, said secure object comprising...
2016/0188493 INFORMATION PROCESSING APPARATUS
According to an embodiment, an information processing apparatus includes a plurality of cores, a shared resource that can be shared by the plurality of cores,...
2016/0188492 Memory Protection with Non-Readable Pages
A method includes, in various implementations, regulating a memory region for execute-only access, storing a set of instructions in the memory region,...
2016/0188491 APPARATUS AND METHOD FOR ASYNCHRONOUS TILE-BASED RENDERING CONTROL
An apparatus and method are described for asynchronous tile-based rendering control. In one embodiment of the invention, there is a delay between when the...
2016/0188490 COST-AWARE PAGE SWAP AND REPLACEMENT IN A MEMORY
Memory eviction that recognizes not all evictions have an equal cost on system performance. A management device keeps a weight and/or a count associated with...
2016/0188489 ATOMIC MEMORY OPERATIONS ON AN N-WAY LINKED LIST
Computer-implemented methods for pushing or popping an element on to of off of an N-way linked list in a computer memory may include one or more atomic memory...
2016/0188488 STORING A SYSTEM-ABSOLUTE ADDRESS (SAA) IN A FIRST LEVEL TRANSLATION LOOK-ASIDE BUFFER (TLB)
Embodiments relate to a method, system and computer program product for storing a system-absolute address (SAA) in a first level look-aside buffer (TLB). In...
2016/0188487 REDUNDANT DISK ARRAY USING HETEROGENEOUS DISKS
A redundant disk array method includes allocating identically sized logical blocks of storage units together to form a stripe on each of several data storage...
2016/0188486 Cache Accessed Using Virtual Addresses
A computer architecture provides a memory cache that is accessed not by physical addresses but by virtual addresses directly from running processes....
2016/0188485 PROCESSING PAGE FAULT EXCEPTIONS IN SUPERVISORY SOFTWARE WHEN ACCESSING STRINGS AND SIMILAR DATA STRUCTURES...
Embodiments are directed to a method of accessing a data frame, wherein a first portion of the data frame is in a first memory block, and wherein a second...
2016/0188484 SYSTEM AND METHODS EXCHANGING DATA BETWEEN PROCESSORS THROUGH CONCURRENT SHARED MEMORY
A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a...
2016/0188483 PROCESSING PAGE FAULT EXCEPTIONS IN SUPERVISORY SOFTWARE WHEN ACCESSING STRINGS AND SIMILAR DATA STRUCTURES...
Embodiments are directed to a method of accessing a data frame, wherein a first portion of the data frame is in a first memory block, and wherein a second...
2016/0188482 METHOD AND SYSTEM FOR DYNAMIC OPERATING OF THE MULTI-ATTRIBUTE MEMORY CACHE BASED ON THE DISTRIBUTED MEMORY...
Provided herein is a method for dynamic operating of a multi-attribute memory cache based on a distributed memory integration framework, the method including...
2016/0188481 Integrated Main Memory And Coprocessor With Low Latency
System, method, and apparatus for integrated main memory (MM) and configurable coprocessor (CP) chip for processing subset of network functions. Chip supports...
2016/0188480 EXTRACT TARGET CACHE ATTRIBUTE FACILITY AND INSTRUCTION THEREFOR
A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for...
2016/0188479 INSTRUCTION AND LOGIC TO TEST TRANSACTIONAL EXECUTION STATUS
Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to...
2016/0188478 MANAGING METADATA FOR CACHING DEVICES DURING SHUTDOWN AND RESTART PROCEDURES
A computer program product, system, and method for managing metadata for caching devices during shutdown and restart procedures. Fragment metadata for each...
2016/0188477 ELECTRONIC SYSTEM WITH DATA MANAGEMENT MECHANISM AND METHOD OF OPERATION THEREOF
An electronic system includes: a master controller configured to: monitor an execution of a user program, and generate a pre-fetching hint; a cluster node,...
2016/0188476 HARDWARE PREFETCHER FOR INDIRECT ACCESS PATTERNS
Two techniques address bottlenecking in processors. The first is indirect prefetching. The technique can be especially useful for graph analytics and sparse...
2016/0188475 Concurrent Execution of Critical Sections by Eliding Ownership of Locks
Critical sections of multi-threaded programs, normally protected by locks providing access by only one thread, are speculatively executed concurrently by...
2016/0188474 HARDWARE/SOFTWARE CO-OPTIMIZATION TO IMPROVE PERFORMANCE AND ENERGY FOR INTER-VM COMMUNICATION FOR NFVS AND...
Methods and apparatus implementing Hardware/Software co-optimization to improve performance and energy for inter-VM communication for NFVs and other...
2016/0188473 COMPRESSION OF HARDWARE CACHE COHERENT ADDRESSES
Compression of address bits within a cache coherent subsystem of a chip is performed, enabling a cache coherent subsystem to avoid transmitting, storing, and...
2016/0188472 DISTRIBUTED IMPLEMENTATION FOR CACHE COHERENCE
A distributed implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The distinct...
2016/0188471 CONFIGURABLE SNOOP FILTERS FOR CACHE COHERENT SYSTEMS
A cache coherent system includes a directory with more than one snoop filter, each of which stores information in a different set of snoop filter entries. Each...
2016/0188470 PROMOTION OF A CACHE LINE SHARER TO CACHE LINE OWNER
A system and method for performing coherent cache snoops whereby a single or limited number of sharing coherent agents are snooped for a data access. A...
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