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Patent # Description
2016/0197068 Power Gating for Three Dimensional Integrated Circuits (3DIC)
Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure....
2016/0197067 Contoured Package-on-Package Joint
A contoured package on package joint and a method for making the same are disclosed herein. A method for forming a device comprises providing a substrate...
2016/0197066 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
An improvement is achieved in the reliability of a semiconductor device by preventing a dielectric breakdown between two semiconductor chips facing each other....
2016/0197065 EMBEDDED MEMORY AND POWER MANAGEMENT SUBPACKAGE
Embodiment of the present disclosure describe integrated circuit package assemblies that allow for relatively short connections between devices such as a...
2016/0197064 OPTOELECTRONIC DEVICE COMPRISING LIGHT-EMITTING DIODES
An optoelectronic device including a semiconductor substrate that is optionally doped with a first type of conductivity; a first semiconductor region that is...
2016/0197063 SEMICONDUCTOR PACKAGE WITH PACKAGE-ON-PACKAGE STACKING CAPABILITY AND METHOD OF MANUFACTURING THE SAME
The present invention relates to a method of making a semiconductor package with package-on-package stacking capability. In accordance with a preferred...
2016/0197062 Light-Emitting Device With Multi-Color Temperature And Multi-Loop Configuration
A light-emitting device with multi-color temperature and multi-loop configuration is provided. The light-emitting device may include a substrate, multiple...
2016/0197061 Packaging a Substrate with an LED into an Interconnect Structure Only Through Top Side Landing Pads on the...
Standardized photon building blocks are packaged in molded interconnect structures to form a variety of LED array products. No electrical conductors pass...
2016/0197060 PACKAGE WITH MULTIPLE PLANE I/O STRUCTURE
A embodiment package includes a three dimensional integrated circuit (3D IC) with first input/output pads on a first side and second input/output pads on a...
2016/0197059 Semiconductor Device and Method of Forming Shielding Layer over Integrated Passive Device Using Conductive Channels
A semiconductor device is made by providing a substrate, forming a first insulation layer over the substrate, forming a first conductive layer over the first...
2016/0197058 STUB MINIMIZATION USING DUPLICATE SETS OF TERMINALS FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS
A microelectronic assembly can include a microelectronic package connected with a circuit panel. The package has a microelectronic element having a front face...
2016/0197057 SEMICONDUCTOR PACKAGES
The invention relates to a semiconductor package that includes a connection member disposed at one side of the semiconductor chip, an insulating layer covering...
2016/0197056 Die and Manufacturing Method for a Die
The present invention refers to a die (1) with an improved crack detecting structure for a predefined area of the die comprising an electrical conductive path...
2016/0197055 3D INTEGRATED CIRCUIT (3DIC) STRUCTURE AND METHOD OF MAKING SAME
An embodiment bonded integrated circuit (IC) structure includes a first IC structure and a second IC structure bonded to the first IC structure. The first IC...
2016/0197054 IGBT DEVICE AND METHOD FOR PACKAGING WHOLE-WAFER IGBT CHIP
An IGBT device and a method for packaging a whole-wafer IGBT chip. The IGBT device comprises: an entire wafer IGBT chip, the upper surface thereof comprising a...
2016/0197053 Ball Grid Array Rework
Embodiments relate to a method and apparatus for rework of a BGA package. Memory shape material is placed adjacent to a plurality of solder joints of the...
2016/0197052 BUMP-EQUIPPED ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING BUMP-EQUIPPED ELECTRONIC COMPONENT
A bump-equipped electronic component includes a circuit substrate and first and second bumps which are disposed on a principal surface of the circuit substrate...
2016/0197051 Chip And Electronic Device
A chip includes a substrate and a die that are wrapped together by means of a packaging process. Multiple substrate cables corresponding to attachment points...
2016/0197050 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
A manufacturing method of a BGA, includes the steps of: providing a semiconductor chip having electrode pads; and removing a natural oxide film formed on the...
2016/0197049 Hybrid Bonding with Air-Gap Structure
A package component includes a surface dielectric layer having a first planar surface, and a metal pad in the surface dielectric layer. The metal pad includes...
2016/0197048 THREE-DIMENSIONAL INTEGRATED STRUCTURE COMPRISING AN ANTENNA CROSS REFERENCE TO RELATED APPLICATIONS
A three-dimensional integrated structure includes a support element, an interface device connected to the support element by a first electrically conductive...
2016/0197047 INTEGRATED CIRCUIT WITH SENSOR AND METHOD OF MANUFACTURING SUCH AN INTEGRATED CIRCUIT
Disclosed is an integrated circuit comprising a substrate carrying a plurality of circuit elements; a metallization stack interconnecting said circuit...
2016/0197046 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A device region (17) is formed at a central part of a semiconductor wafer (2) and a ring-shaped reinforced portion (18) which is thicker than the device region...
2016/0197045 SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD FOR SAME
A semiconductor device includes: a substrate on which a first contact portion is formed; a lower shield plate provided above the substrate to avoid the first...
2016/0197044 METHOD AND APPARATUS THAT PROCESSES AN OPTOELECTRONIC COMPONENT
A method of processing an optoelectronic component includes a light source having at least one luminous area formed by one or a plurality of light emitting...
2016/0197043 SUPPORT STRUCTURE FOR BARRIER LAYER OF SEMICONDUCTOR DEVICE
Among other things, one or more support structures and techniques for forming such support structures within semiconductor devices are provided. The support...
2016/0197042 SEMICONDUCTOR DEVICES INCLUDING SPACERS
A spacer covering a sidewall of a contact plug includes a relatively more damaged first portion and a relatively less damaged second portion. An interface of...
2016/0197041 MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
A memory device comprises a first conductive stripe, a first memory layer, a first conductive pillar, a first dielectric layer and a first conductive plug. The...
2016/0197040 POWER LINE STRUCTURE FOR SEMICONDUCTOR APPARATUS
A semiconductor apparatus has one or more semiconductor chips. The semiconductor apparatus may include a power supply pad; power lines disposed on one side of...
2016/0197039 STACKED VIA STRUCTURE FOR METAL FUSE APPLICATIONS
A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the...
2016/0197038 SELF-ALIGNED VIA INTERCONNECT STRUCTURES
A self-aligned via interconnect structures and methods of manufacturing thereof are disclosed. The method includes forming a wiring structure in a dielectric...
2016/0197037 LOCALIZED HIGH DENSITY SUBSTRATE ROUTING
Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus...
2016/0197036 ELECTRONIC DEVICE INCLUDING A SEMICONDUCTOR MEMORY UNIT THAT INCLUDES CELL MATS OF A PLURALITY OF PLANES...
An electronic device includes a semiconductor memory. The semiconductor memory includes a plurality of planes vertically stacked over a substrate. Each plane...
2016/0197035 STACKED MULTILAYER STRUCTURE AND MANUFACTURING METHOD THEREOF
A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers...
2016/0197034 PACKAGE CARRIER
A package carrier suitable for carrying at least a chip is provided. The package carrier includes an insulating layer, a patterned circuit layer, a plurality...
2016/0197033 COMPOUND CARRIER BOARD STRUCTURE OF FLIP-CHIP CHIP-SCALE PACKAGE AND MANUFACTURING METHOD THEREOF
A compound carrier board structure of Flip-Chip Chip-Scale Package and manufacturing method thereof provides a baseplate with a penetrating rectangular opening...
2016/0197032 SEMICONDUCTOR DEVICE WITH REDISTRIBUTION LAYERS ON PARTIAL ENCAPSULATION AND NON-PHOTOSENSITIVE PASSIVATION LAYERS
A semiconductor device with redistribution layers on partial encapsulation is disclosed and may include a semiconductor die having a first surface, a second...
2016/0197031 SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE INCLUDING THE SAME, AND METHOD OF MOUNTING SEMICONDUCTOR DEVICE
An electronic device including a semiconductor device and a method of mounting a semiconductor device are provided. The semiconductor device includes a base...
2016/0197030 INTEGRATED CIRCUIT (IC) PACKAGE WITH THICK DIE PAD, AND ASSOCIATED METHODS
An integrated circuit (IC) package includes a die pad and an IC die secured on the die pad. The IC die had outer edges aligned with outer edges of the die pad....
2016/0197029 Semiconductor Device and Method
A semiconductor device and method are provided which utilizes a single mask to form openings for both a through substrate via as well as for a through...
2016/0197028 SEMICONDUCTOR MODULE AND INVERTER DEVICE
In a semiconductor module of the invention, a heat sink has a convex portion in which a convex plane has an area smaller than a joint area to the joint layer,...
2016/0197027 SEMICONDUCTOR DEVICE STRUCTURES COMPRISING POLYCRYSTALLINE CVD DIAMOND WITH IMPROVED NEAR-SUBSTRATE THERMAL...
A semiconductor device structure comprising: a layer of III-V compound semiconductor material; a layer of polycrystalline CVD diamond material; and an...
2016/0197026 Thermal vias disposed in a substrate without a liner layer
An apparatus relating generally to a substrate is disclosed. In such an apparatus, the substrate has formed therein a plurality of vias. A liner layer is...
2016/0197025 Method of Fabricating an Electronic Device
A silicone composition contains I) a shrink additive and II) a curable polyorganosiloxane composition. A method for fabricating an electronic device includes...
2016/0197024 SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE
A semiconductor device manufacturing method includes a step of preparing a semiconductor unit, having a first main surface including a heat releasing portion...
2016/0197023 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor layer, a first conductor film, a second conductor film, and a first protective film. The semiconductor layer...
2016/0197022 Semiconductor Device and Method of Forming Sacrificial Adhesive Over Contact Pads of Semiconductor Die
A semiconductor wafer contains a plurality of semiconductor die each having a plurality of contact pads. A sacrificial adhesive is deposited over the contact...
2016/0197021 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
When VC inspection for a TEG is performed, it is easily detected whether any failure of a contact plug occurs or not by increasing an emission intensity of a...
2016/0197020 FILM FOR SEMICONDUCTOR PACKAGE, SEMICONDUCTOR PACKAGE USING FILM AND DISPLAY DEVICE INCLUDING THE SAME
A semiconductor package may include a first output test pad and a second output test pad disposed on a first surface of an insulating film, and a semiconductor...
2016/0197019 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device includes: a plurality of stacked semiconductor layers; a plurality of composite doped regions separately and parallelly disposed in a...
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