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Patent # Description
2016/0197018 INTEGRATED CIRCUIT COMPRISING PMOS TRANSISTORS WITH DIFFERENT VOLTAGE THRESHOLDS
There is provided a method for the manufacture of an integrated circuit, including a substrate and an insulating layer formed on the substrate; a first pMOS...
2016/0197017 FINFET DEVICE AND FABRICATION METHOD THEREOF
A method for forming a FinFET device is provided. The method includes providing a substrate having a first region and a second region; and forming a plurality...
2016/0197016 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate with an insulating layer formed thereon. The...
2016/0197015 HYBRID WAFER DICING APPROACH USING A POLYGON SCANNING-BASED LASER SCRIBING PROCESS AND PLASMA ETCH PROCESS
Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor...
2016/0197014 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING THROUGH SILICON PLUGS
A method of making a semiconductor device is provided including forming a first opening and a second opening in a first surface of a substrate. A conductive...
2016/0197013 SELF-ALIGNED VIA INTERCONNECT STRUCTURES
A self-aligned via interconnect structures and methods of manufacturing thereof are disclosed. The method includes forming a wiring structure in a dielectric...
2016/0197012 Semiconductor Devices and Methods of Manufacture Thereof
Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming...
2016/0197011 Subtractive Self-Aligned Via and Plug Patterning for Back End of Line (BEOL) Interconnects
Subtractive self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an...
2016/0197010 SEMICONDUCTOR DEVICE WITH REDUCED VIA RESISTANCE
A method of fabricating a semiconductor interconnect structure by providing a semiconductor structure that includes two dielectric layers. The first dielectric...
2016/0197009 Device and Method for Stopping an Etching Process
A method for etching a layer assembly, the layer assembly including an intermediate layer sandwiched between an etch layer and a stop layer, the method...
2016/0197008 METHOD FOR MANUFACTURING BONDED WAFER
A method for manufacturing bonded wafer including: producing bonded wafer having thin-film on its base wafer by an ion implantation delamination method, and...
2016/0197007 METHOD OF PRODUCING BONDED WAFER
A method of producing a bonded wafer in which wafers each having a cutout portion are used as a bond wafer and a base wafer, and either or both of settings of...
2016/0197006 METHOD FOR LOCATING DEVICES
The disclosure relates to a process for locating devices, the process comprising the following steps: a) providing a carrier substrate comprising: a device...
2016/0197005 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
The present invention provides a semiconductor structure including a substrate, at least one fin group and a plurality of sub-fin structures disposed on the...
2016/0197004 ELECTRICALLY INSULATED FIN STRUCTURE(S) WITH ALTERNATIVE CHANNEL MATERIALS AND FABRICATION METHODS
Semiconductor structures and fabrication methods are provided which includes, for instance, fabricating a semiconductor fin structure by: providing a fin...
2016/0197003 SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD OF FABRICATING THE SAME
A method of fabricating a semiconductor device and a semiconductor device formed by the method. The method includes form a stack conductive structure by...
2016/0197002 INTERCONNECT STRUCTURES INCORPORATING AIR-GAP SPACERS
A dual damascene article of manufacture comprises a trench containing a conductive metal column where the trench and the conductive metal column extend down...
2016/0197001 PROCESSING CHAMBER
Embodiments of the present disclosure provide a processing chamber with a top, a bottom, and a sidewall coupled together to define an enclosure, a gas...
2016/0197000 SINGLE-WAFER-TYPE CLEANING APPARATUS
A single-wafer-type cleaning apparatus is provided. The single-wafer-type cleaning apparatus is configured to be capable of controlling electrostatic charges...
2016/0196999 WAFER HOLDER AND METHOD FOR MANUFACTURING THE SAME
A wafer holder 10 includes a resin adhesive layer 16 between a ceramic electrostatic chuck 12 and a metal cooling plate 14. The adhesive layer 16 includes a...
2016/0196998 MICRO DEVICE TRANSFER HEAD ARRAY
A micro device transfer head array and method of forming a micro device transfer array from an SOI substrate are described. In an embodiment, the micro device...
2016/0196997 SUBSTRATE CARRIER WITH INTEGRATED ELECTROSTATIC CHUCK
A substrate carrier adapted to use in a processing system includes an electrode assembly and a support base. The electrode assembly is configured to generate...
2016/0196996 ADSORPTION DEVICE AND CONTROL METHOD THEREOF
The present invention provides an adsorption device and a control method thereof. The adsorption device includes a loading module, a power supply module, a...
2016/0196995 SEMICONDUCTOR MANUFACTURING APPARATUS AND SEMICONDUCTOR MANUFACTURING METHOD
In one embodiment, a semiconductor manufacturing apparatus includes a wafer setting module on which a wafer is to be set. The apparatus further includes a...
2016/0196994 Reticle Transfer System and Method
A fabrication system comprises placing an internal buffer at a default position of a local system, wherein the default position is a first boundary between a...
2016/0196993 PACKING STRUCTURE FOR PACKING SUBSTRATE STORING CONTAINER
An upper cushioning material is placed on a substrate storing container in a packing box. The substrate storing container is placed on a lower cushioning...
2016/0196992 LAMP DRIVER FOR LOW PRESSURE ENVIRONMENT
Embodiments of the present disclosure relate to a lamp driver for lamps used as a source of heat radiation in a thermal processing chamber. The lamp driver...
2016/0196991 CIRCULATION COOLING AND HEATING DEVICE
A circulating cooling/heating device configured to cool and heat a circulating fluid supplied to a chamber in plasma-etching equipment includes: a heat...
2016/0196990 METHOD OF FABRICATING SEMICONDUCTOR PACKAGE
A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer...
2016/0196989 Baseplate for an electronic module and method of manufacturing the same
Various embodiments provide methods for manufacturing a baseplate for an electronic module and an electronic module comprising a baseplate, wherein the...
2016/0196988 EMBEDDED SEMICONDUCTIVE CHIPS IN RECONSTITUTED WAFERS, AND SYSTEMS CONTAINING SAME
A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are...
2016/0196987 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for...
2016/0196986 BALL GRID ARRAY PACKAGE SUBSTRATE WITH THROUGH HOLES AND METHOD OF FORMING SAME
In accordance with an embodiment, there is provided a substrate of a ball grid array package that includes a first layer including reinforcement fibers. The...
2016/0196985 METHOD AND APPARATUS FOR ANISOTROPIC TUNGSTEN ETCHING
Methods for anisotropically etching a tungsten-containing material (such as doped or undoped tungsten metal) include cyclic treatment of tungsten surface with...
2016/0196984 ISOTROPIC ATOMIC LAYER ETCH FOR SILICON AND GERMANIUM OXIDES
Methods for controlled isotropic etching of layers of silicon oxide and germanium oxide with atomic scale fidelity are provided. The methods make use of a...
2016/0196983 SEMICONDUCTOR DEVICE WITH NON-LINEAR SURFACE
A semiconductor device includes a channel having a first linear surface and a first non-linear surface. The first non-linear surface defines a first external...
2016/0196982 METHOD OF FABRICATING SEMICONDUCTOR DEVICE
A method of fabricating a semiconductor device includes forming line patterns over a first region of an etch target layer and a pre-pad pattern over second and...
2016/0196981 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device including a wafer using a plasma etching device which includes a chamber, a chuck provided in the chamber to...
2016/0196980 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
The present invention provides a technology capable of removing impurities remaining in a thin film when the film is formed and modifying a characteristic of...
2016/0196979 SELF-ALIGNED INSULATED FILM FOR HIGH-K METAL GATE DEVICE
An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, a metal gate structure over the semiconductor substrate and the...
2016/0196978 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING DEVICE, AND RECORDING MEDIUM
A method for manufacturing a semiconductor device, including: forming a metal carbide film including a first metal element and a second metal element on a...
2016/0196977 SILANE AND BORANE TREATMENTS FOR TITANIUM CARBIDE FILMS
Methods of treating metal-containing thin films, such as films comprising titanium carbide, with a silane/borane agent are provided. In some embodiments a film...
2016/0196976 Method for tuning the effective work function of a metal
The disclosed technology generally relates to integrated circuit devices and methods of forming the same, and more particularly to metal electrodes whose...
2016/0196975 Method of Providing An Implanted Region In A Semiconductor Structure
According to an aspect of the present inventive concept there is provided a method of providing an implanted region in a semiconductor structure including a...
2016/0196974 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
Semiconductor devices and methods of manufacturing the semiconductor devices are provided. The semiconductor devices may include a first line pattern that...
2016/0196973 REDUCED EXTERNAL RESISTANCE FINFET DEVICE
The present invention relates generally to semiconductor devices, and more particularly, to a structure and method of reducing external resistance within fin...
2016/0196972 FABRICATION OF III-V-ON-INSULATOR PLATFORMS FOR SEMICONDUCTOR DEVICES
Embodiments of the present invention provide III-V-on-insulator (IIIVOI) platforms for semiconductor devices and methods for fabricating the same. According to...
2016/0196971 METHOD OF FORMING GATE DIELECTRIC LAYER FOR MOS TRANSISTOR
A method of forming a gate dielectric layer for a MOS transistor includes the following steps. A gate dielectric layer is formed on a substrate. A nitrdation...
2016/0196970 METHODS FOR FORMING DOPED SILICON OXIDE THIN FILMS
The present disclosure relates to the deposition of dopant films, such as doped silicon oxide films, by atomic layer deposition processes. In some embodiments,...
2016/0196969 ISOTROPIC ATOMIC LAYER ETCH FOR SILICON OXIDES USING NO ACTIVATION
Methods for controlled isotropic etching of layers of silicon oxide and germanium oxide with atomic scale fidelity are provided. The methods make use of NO...
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